A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

Inoue, Ryoichi; Hosokawa, Toshinori; Fujiwara, Hideo

doi:10.1109/ats.2008.32

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…A refined representation is used in the test generation algorithm to simplify and speed up search process of test sequences. Hosokawa et al propose in [53,54] both a fault-independent test generation method and a fault-dependent test generation method for state observable FSMs.…”

Section: F Fault Models Based On Hierarchical Structurementioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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Section: F Fault Models Based On Hierarchical Structurementioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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“…Since structural test alone cannot provide the desired defect coverage [1], functional test is also used in industry to target defects that are not detected by structural test [2]. Therefore, considerable research effort has been devoted to register-transfer (RT)-level fault modeling [3]- [4], test generation [5]- [7], design-for-testability (DFT) [8]- [10], [12]- [14], and test evaluation methods.…”

mentioning

confidence: 99%

“…A number of methods have been presented in the literature for test generation at RT-level [5]- [7]. However, they usually suffer from low fault coverage due to the lack of gate-level information or due to the poor testability of the design.…”

mentioning

confidence: 99%

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage

Sanyal

Chakrabarty

Yilmaz

et al. 2010

2010 IEEE International Test Conference

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Abstract-Functional test sequences play an important role in manufacturing test for targeting defects that are not detected by structural test. In practice, functional tests are often derived from existing design-verification test sequences and they suffer from low defect coverage. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a non-scan DFT technique at the register-transfer (RT) level that tackles the above problem in three steps. It can be used to increase the defect coverage for scan-based designs by making functional test sequences more effective in native (non-scan) mode. The proposed method selects a small set of control points, and through an efficient branch-and-bound strategy, determines an effective set of truth assignments to these control points (also called test modes). The original functional test is expanded by applying the same functional test sequence once with each selected test mode.

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