A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Gómez, R.; Girón, Alejandro; Champac, Victor

doi:10.1007/s10836-008-5085-z

Cited by 9 publications

(7 citation statements)

References 32 publications

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“…Without loss of generality, a zero value has been considered for the trapped gate charge. A test vector generation methodology called Opens Vector Generator (OPVEG) [8] is used to obtain the set of test vectors. OPVEG selects those open locations (for example, vias) susceptible to be significantly influenced by their coupling signals.…”

Section: Validationmentioning

confidence: 99%

“…Using a commercial ATPG tool [8], OPVEG attempts to generate test vectors for all the selected opens setting favorable logic conditions at the coupled signals. When the detection probability is very low, OPVEG tries to improve the detection probability by generating a new test vector with more favorable logic conditions at the coupled signals.…”

Section: Validationmentioning

confidence: 99%

“…The computing time to obtain the detection probability using the statistical analysis increases moderately with respect to the case without process variations. Information about the computing times required to obtain the test vectors using OPVEG can be found in [8].…”

Section: Validationmentioning

confidence: 99%

“…Recently, it has been found that the gate tunneling leakage may influence the interconnect open behavior in some technologies [7], but this effect is not considered in this brief. Manuscript Detectability conditions as well as test generation methods for interconnect opens have been proposed in [6] and [8]- [11]. For example, reducing the power supply voltage during testing allows the detection of some defects missed at nominal supply voltage condition [12].…”

Section: Introductionmentioning

confidence: 99%

“…Previously published works use an interconnect open model with nominal values of the electrical parameters to determine the defect behavior [4], [5], [8], [9]. However, in nanometer technologies, the impact of process parameter variations has become significant.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Moreno

Renovell

Champac

2016

IEEE Trans. VLSI Syst.

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Interconnect opens are a major class of defects found in today's nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low V DD in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

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Section: Validationmentioning

confidence: 99%

Section: Validationmentioning

confidence: 99%

Section: Validationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Moreno

Renovell

Champac

2016

IEEE Trans. VLSI Syst.

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Identification of Logic Paths Influenced by Severe Coupling Capacitances

et al. 2020

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Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow

Chen

Chang

Wen

2012

IET Comput. Digit. Tech.

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As an open defect occurs in one wire segment of the circuit, different logic values on the coupling wires of the physical layout may result in different faulty behaviours, which are so called the Byzantine effect. Many previous researches focus on the test and diagnosis of open defects but the pattern diagnosability has not properly addressed. Therefore in this study, a highresolution diagnostic framework for open defects is proposed and consists of a diagnostic test-pattern generation (DTPG) and its diagnosis flow. The branch-and-bound search associated with controllability analysis is incorporated in satisfiability-based DTPG to generate patterns for the target segment. Later, a precise diagnosis flow constructs the list of defect candidates in a dictionary-based fashion followed by an inject-and-evaluate analysis to greatly reduce the number of candidates for silicon inspection. Experimental results show that the proposed framework runs efficiently and deduces nearly one candidate for each open-segment defect on average among all ISCAS'85 benchmark circuits.

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A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Cited by 9 publications

References 32 publications

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations

Identification of Logic Paths Influenced by Severe Coupling Capacitances

Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow

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