A test methodology for finite state machines using partial scan design

Min, Hyoung Bok; Rogers, William A.

doi:10.1007/bf00137250

Cited by 15 publications

(7 citation statements)

References 18 publications

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“…Following up on the idea, Min and Rogers [27] obtained a simple combinational ATPG model in which all FFs are shorted during test generation. A test vector repeated dseq times detects the fault in the sequential circuit.…”

Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-It is known that the complexity of automatic test pattern generation (ATPG) for acyclic sequential circuits is similar to that of combinational ATPG. The general problem, however, requires time-frame expansion and multiple-fault detection and hence does not allow the use of available combinational ATPG programs. The first contribution of this work is a combinational single-fault ATPG method for the most general class of acyclic sequential circuits. Without inserting any real hardware, we create a functionally equivalent "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs and gates are duplicated in this model, which is converted into a combinational circuit by shorting all flip-flops. A test vector obtained by a combinational ATPG program for a fault in this combinational circuit is transformed into a test sequence to detect a corresponding fault in the original sequential circuit. A combinational ATPG program finds tests for all but a small set of faults that must be explicitly detected as multiple-faults. Those are modeled for ATPG using the second contribution of this work, which is a generalized method to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most + 3 modeling gates for a fault of multiplicity . We show that the modeled circuit is functionally equivalent to the original circuit and the targeted multiple fault is equivalent to the modeled single stuck-at fault. Benchmark results show at least an order of magnitude saving in the ATPG CPU time by the new combinational method over sequential ATPG.Index Terms-Acyclic sequential circuit, automatic test pattern generation (ATPG), balanced model, combinational test generation, design for test (DFT), partial scan, test.

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Section: Circuit Subclasses and Atpg Methodsmentioning

confidence: 99%

Combinational automatic test pattern generation for acyclic sequential circuits

Kim

Agrawal

Saluja

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We use vector holding to enhance the fault coverage [8,12,13,23]. It involves holding input vectors constant for several clock cycles while applying the system clock to the circuit under test.…”

Section: Holder Circuitmentioning

confidence: 99%

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns

Yogi

Agrawal

2008

2008 17th Asian Test Symposium

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ATPG patterns of a digital sequential circuit contain temporally and spatially ordered bits as well as random (or don't care) bits. We synthesize BIST hardware that mimics these characteristics by controlled mixing of spectral components and noise. A Hadamard digital wave generator circuit produces all required spectral sequences and a weighted pseudorandom bit generator provides random bits. While these two blocks serve the entire circuit under test, specific to each primary input are two small blocks, one that combines the required Hadamard sequences in proper proportions and the other a randomizer that adds the required amount of noise if necessary. As an example, the FlexTest ATPG produced 55110 patterns for s38417, detecting 15472 of 31180 stuck-at faults. Sixty four-thousand of our BIST patterns detected 17020 faults as compared to 4244 detected by a previously reported spectral BIST method utilizing similar hardware overhead.

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“…This is significantly different from a previous combinational model [20] where repeated test patterns were used. Our method detects all sequentially detectable faults, and also identifies all sequentially untestable faults to achieve maximum possible fault efficiency faster than the conventional sequential test generation approach.…”

Section: Resultsmentioning

confidence: 65%

“…For the cyclic ISCAS 89 benchmark circuits, we scanned minimal sets of FFs to make the kernel circuit acyclic. Using improved algorithms, in most cases wt: scanned fewer FFs than reported by Min and Rogers [20].…”

Section: Resultsmentioning

confidence: 78%