A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

Lien, Wei-Cheng; Lee, Kuen-Jong; Hsieh, Tong-Yu

doi:10.1109/ats.2012.11

Cited by 11 publications

(6 citation statements)

References 19 publications

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“…The area overhead of a ROM includes an address decoder and ROM cells. Because the actual area of a ROM cell under the TSMC-90 nm technology is not available to us, we refer to the work in [5,7,11] where a ROM cell is estimated to have a 0.25 gate count. From Table 2 we can see that in almost all cases our method has smaller area overhead.…”

Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

“…The storage of deterministic patterns in an on-chip ROM reduces the tester memory requirement and hence test-equipment cost. To further reduce the size of the ROM reseeding techniques [4,6,7,9,11,17] are widely adopted to compress the required test data into a few seeds of small size. The seeds can then be decompressed by an LFSR or similar hardware during test-application time.…”

Section: Introductionmentioning

confidence: 99%

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Efficient LFSR Reseeding Based on Internal-Response Feedback

et al. 2014

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LFSR reseeding techniques are widely adopted in logic BIST to enhance fault detectability and shorten testapplication time for integrated circuits. In order to achieve complete fault coverage, previous reseeding methods often need a prohibitive amount of memory to store all required seeds. In this paper, a new LFSR reseeding technique is presented, which employs the responses of internal nets of the circuit itself as the control signals for changing LFSR states. A novel reseeding architecture containing a netselection logic module and an LFSR with some inversion logic is presented to generate all the required seeds on-chip in real time with no external or internal storage requirement. Experimental results on ISCAS and large ITC circuits show that the presented technique can achieve 100 % fault coverage with short test time by using only 0.23 -2.75 % of internal nets and with 2.35 -4.56 % gate area overhead on average for reseeding control without degrading the original circuit performance.

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Section: Results Of Proposed Reseeding Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient LFSR Reseeding Based on Internal-Response Feedback

et al. 2014

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“…Several works use/assume this proposition for the selection of their characteristic polynomial. Some of these works are seed compression [15], on-line seed loading [14], [12], multiple polynomial LFSR structures [6], [10], multiple seeds to generate one or more tests [13], LFSR reseeding with additional hardware to control the LFSR behavior [8], [18], [2], [19], and reseeding targeting additional features like defect-oriented reseeding [9], [24], unmodeled faults reseeding [26] and low-power dissipation [17], [16]. What is common in all these methodologies is that the polynomial used to implement the LFSR is fixed a priori in an arbitrary manner.…”

Section: Introductionmentioning

confidence: 99%

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Acevedo

Kagaris

2016

IEEE Trans. Comput.

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In built-in test pattern generation and test set compression, an LFSR is usually employed as the on-chip generator with an arbitrarily selected characteristic polynomial of degree equal, according to a popular rule, to Smax + 20, where Smax is the maximum number of specified bits in any test cube of the test set. By fixing the polynomial a priori a linear system only needs to be solved to compute the required LFSR initial states (seeds) to generate the target test cubes, but the disadvantage is that the polynomial degree (length of the LFSR and seed bit size) may be too large and the fault coverage cannot be guaranteed. In this paper we address the problem of computing a polynomial of small degree directly from the given test set without having to solve multiple non-linear systems and fixing a priori the polynomial degree. The proposed method uses an adaptation of the BerlekampMassey algorithm and the Sidorenko-Bossert theorem to perform the computation. In addition, the method guarantees (by design) that all the test cubes in the given test set are generated, thereby achieving 100% coverage, which cannot be guaranteed under the "trialand-error" Smax + 20 rule. Experimental results verify the advantages that the proposed methodology offers in terms of reduced polynomial degree and 100% coverage.

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“…Linear compression schemes are very efficient in exploiting unspecified bits in the test cubes to achieve a large amount of compression. Several techniques were proposed based on LFSR reseeding to reduce the test data volume [4,5,6]. The LFSR reseeding techniques make use of the many unspecified bits in deterministic test patterns.…”

Section: Introductionmentioning

confidence: 99%

Test Data Compression with Alternating Equal-Run-Length Coding

Sivanantham¹,

S²,

Ramki³

et al. 2018

IJET

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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

Cited by 11 publications

References 19 publications

Efficient LFSR Reseeding Based on Internal-Response Feedback

Efficient LFSR Reseeding Based on Internal-Response Feedback

On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern Generation

Test Data Compression with Alternating Equal-Run-Length Coding

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