2019 27th Iranian Conference on Electrical Engineering (ICEE) 2019
DOI: 10.1109/iraniancee.2019.8786741
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A Time-based All-Digital Analog to Digital converter for IOT Applications

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Cited by 5 publications
(5 citation statements)
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“…However, the sampling rate is very small (50MS/s). In [34], although the proposed VTC achieves a better dynamic range of 400mV, the power consumption of this design is relatively high (3.35mW). In [35], a fully digital time-based ADC is proposed to reduce the chip area at which the power consumption is reduced to 380μW.…”
Section: Novel Trends and Future Workmentioning
confidence: 99%
See 1 more Smart Citation
“…However, the sampling rate is very small (50MS/s). In [34], although the proposed VTC achieves a better dynamic range of 400mV, the power consumption of this design is relatively high (3.35mW). In [35], a fully digital time-based ADC is proposed to reduce the chip area at which the power consumption is reduced to 380μW.…”
Section: Novel Trends and Future Workmentioning
confidence: 99%
“…A lot of research is done to improve the performance of the VTC circuit. Circuits in [16] and [26][27][28][29][30][31][32][33][34][35] are proposed to overcome the previously mentioned limitations of the conventional VTC circuit. In [16], a linearization circuit is proposed to achieve a maximum linearity error of 2%.…”
Section: Novel Trends and Future Workmentioning
confidence: 99%
“…Sinyal elektronik ini bisa berupa perubahan tegangan ataupun perubahan arus tergantung dengan jenis load cell yang digunakan. Strain gauge adalah pita tipis konduktor yang akan naik tahanan listriknya bila meregang (positive strain/ tension stress) dan turun bila mengerut (negative strain/ compressive stress) [4] [5].…”
Section: B Sensor Load Cellunclassified
“…Many modified VTC circuits have been proposed by researchers [3][4][5][6][7][8][9][10][11][12] to overcome the previously mentioned drawbacks of the conventional VTC circuit. However, these circuits are not sufficiently linear and have low resolution.…”
Section: Introductionmentioning
confidence: 99%
“…However, the maximum linearity error is 2.1% and the modified circuit operates at a low clock frequency of 50 MHz. In Reference [11], a modified VTC is introduced to increase the linearity but the power consumption of this design is high (3.35 mW), and the input dynamic range is limited to 400 mV. In Reference [12], a fully digital time-based ADC is proposed to reduce the chip area at which the power consumption is reduced to 380 µW but still relatively high.…”
Section: Introductionmentioning
confidence: 99%