A Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation

Jiang, Dongyang; Qi, Liang; Sin, Sai-Weng; Maloberti, Franco; Martins, Rui P.

doi:10.1109/jssc.2021.3060859

Cited by 13 publications

(1 citation statement)

References 23 publications

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“…Figure 1 shows the block diagram of a second order discrete-time sigma-delta modulator that is widely used for various applications due to its high power/area efficiency and good stability [14,15]. The circuit level sigma-delta modulator can be divided into analog and digital blocks.…”

Section: Sigma-delta Modulator Non-idealitiesmentioning

confidence: 99%

Macro Model for Discrete-Time Sigma‒Delta Modulators

Lee

2022

Electronics

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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Section: Sigma-delta Modulator Non-idealitiesmentioning

confidence: 99%