A Time-Interleaved Multimode RF-DAC for Direct Digital-to-RF Synthesis

McCue, Jamin J.; Dupaix, Brian; Duncan, Lucas; Mathieu, Brandon; McDonnell, Samantha; Patel, Vaama; Quach, T.; Khalil, Waleed

doi:10.1109/jssc.2016.2521903

Cited by 25 publications

(11 citation statements)

References 32 publications

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“…40 Therefore, we assume that the static power equals the value of P swing . In the state-of-the-art high-speed designs 9,10,19,41 that utilize ΔΣ modulation, the value of β is less than 0.2, while the ratio of P static to P dynamic is less than 0.3. Let us assume that the value of β equals 0.2 while the ratio of P static to P dynamic is 0.3.…”

Section: Configuration With the Highest Dynamic Range Performancementioning

confidence: 99%

“…[1][2][3][4][5][6][7][8][9][10][11] Techniques used to improve the SFDR in high-speed applications rely on more stringent clocking 1,2,12-20 (eg, half-cycle sampling) or increased area [3][4][5][6][7][8]19,[21][22][23][24] (eg, 2 interleaved sub-DACs). One key performance metric for its high-speed and wideband applications is the dynamic linearity, usually evaluated as the spurious-free dynamic range (SFDR).…”

Section: Introductionmentioning

confidence: 99%

“…When the output frequency or the sampling rate goes up, the intersymbol interference (ISI) errors during the switching transition of current sources become one of the main bottlenecks towards a higher SFDR. 1-11 Techniques used to improve the SFDR in high-speed applications rely on more stringent clocking 1,2,12-20 (eg, half-cycle sampling) or increased area [3][4][5][6][7][8]19,[21][22][23][24]…”

mentioning

confidence: 99%

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Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

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Section: Configuration With the Highest Dynamic Range Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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“…However, the size of these circuitry increases proportional to the effective resolution bits of the DACs. For example, in [8], two 3-bit parallel DACs require a 9-bit DAC for amplitude calibration and timing adjustment is done with 5-bit weighted current sources. Therefore, it is practical to lower resolution bits of the I and Q DACs.…”

Section: Architecture Based On 2-path Parallel 1-bit Hp Fir Dacsmentioning

confidence: 99%

“…To reach carrier frequencies up to half the signal sampling frequency of the DAC, f c = f s /2, without including a mixing stage in the DAC, the work in [8] takes as an input a quadrature output signal at 4 f c to a two-path interleaved architecture which has a cascade of a high pass (HP) -modulator and a multi-bit DAC in each of its channel. Image rejection is obtained due to multi-phase clocking of the channels.…”

Section: Introductionmentioning

confidence: 99%

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Gebreyohannes

Frappé

Cathelin

et al. 2018

IEEE Trans. Circuits Syst. I

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This paper presents a novel transmitter architecture which is tailored for low power, all-digital, and high speed implementation. It is based on two-path parallel digital-to-analog converters (DAC) which are driven by 180 • phase-shifted clocks. The architecture operates in high pass mode and extends the output carrier frequency up to half the DAC clock rate. To decrease the number of analog unit current cells in the converter, a lowpass-modulator is used. Since the modulator also converts the input resolution to 1-bit, an inherently-linear digital-toanalog conversion is realized by embedding filtering in the DAC. Furthermore, the finite impulse response DAC transfer function is designed to cancel the-modulator quantization noise. Simulation results at system level demonstrate the robustness of the architecture against random coefficient mismatches, and its suitability for broadband transmissions. The error vector magnitude of the quadrature output is simulated for up to 15% random coefficient mismatch and it maintains a value below −22 dB even when the input signal bandwidths vary from 20 MHz (64-subcarrier OFDM) to 160 MHz (512-subcarrier OFDM). Experimental results are presented to discuss the validity of the proposed all-digital transmitter architecture and to highlight the challenges of implementing it in advanced CMOS nodes. Index Terms-Digital transmitter, high pass FIR DACs, time-interleaving, parallel DACs.

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Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

Roshanpanah,

Torkzadeh,

Hajsadeghi

et al. 2024

Circuits Syst Signal Process

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A Time-Interleaved Multimode RF-DAC for Direct Digital-to-RF Synthesis

Cited by 25 publications

References 32 publications

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs

Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA

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