A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters

Abstract

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice of a suitable technique should be made at the design stage as a result of the analysis of test metrics such as test escapes and yield loss. However, it is very hard to carry out this estimation for analog/RF circuits by using fault simulation techniques. Instead, the estimation of parametric test metrics is made possible by Monte Carlo circuit-level simulations and the construction of statistical models. These models represent the output parameter space of the CUT in which the test metrics are defined. In addition, models of the input parameter space may be required to accelerate the simulations and obtain higher confidence in the DFT choices. In this work, we describe a methodological flow for the selection of most adequate statistical models and several techniques that can be used for obtaining these models. Some of these techniques have been integrated into a Computer-Aided Test (CAT) tool for the automation of the process of test metrics estimation. This estimation is illustrated for the case of a BIST solution for CMOS imager pixels that requires the use of advanced statistical modeling techniques. . 2015. A tool for analog/RF BIST evaluation using statistical models of circuit parameters.

Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model

“…We consider first the case of test escapes T E as defined by Equation (1). If we only consider the population of circuits that pass the test, T E becomes the probability that a circuit is faulty, i.e., the probability to violate at least one specification as follows:…”

“…In the literature, several methods have been proposed to overcome this limitation. They can be divided into two types [1].…”

Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space

“…The training procedure has been carried out using MATLAB and the sequential minimal optimization training method. The kernel used in the procedure is a radial basis function (RBF), which is a standard choice in the field [36]- [38]. The SVM training has been carried out using a 5-folds cross validation together with a grid search to determine the optimum kernel spread, σ, as well as the optimum soft margin parameter, C. A single SVM classifier is capable of dealing with two classes only, so for binning circuits in p bins, p − 1 support vector machines need to be trained.…”

Analog circuits testing using digitally coded indirect measurements

“…Test escape is defined as the probability of classifying a non functional circuit as functional thus being served to the customer [13]. These analog metrics, together with statistical methods, usually serve as a reference to evaluate a given test strategy [14].…”