A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Hamada, M.; Takahashi, Masafumi; Arakida, Hideho; Chiba, A.; Terazawa, T.; Ishikawa, Takashi; Kanazawa, M.; Igarashi, M.; Usami, Kimiyoshi; Kuroda, Tadahiro

doi:10.1109/cicc.1998.695026

Cited by 80 publications

(48 citation statements)

References 2 publications

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“…Here, the supply voltages have been set to V DDH = 0.8 V, and V DDL = 0.5 V. In order to avoid exponentially increase in PN current from the body of MOSFET to the source/drain, we have determined V DDL = 0.5 V directly connected to the body. The value of V DDH has been decided based on the relationship that V DDL = 0.6 ∼ 0.7 V DDH for the minimum power consumption [4]. For these supply voltages, the conditions of forward or reverse body-bias are concretely shown in Fig.…”

Section: Circuit Simulation and Resultsmentioning

confidence: 99%

“…In the dual-V DD scheme, the power saving effect which is actually dependent upon a trade-off between the value of V DDL and the number of V DDL -cells reportedly becomes the maximum when V DDL = 0.6 ∼ 0.7 V DDH [4]. Under this condition, we aim at assigning a larger number of V DDL -cells owing to the lowered threshold voltage by the active body-bias.…”

Section: Dynamic Threshold Voltage Controlmentioning

confidence: 99%

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Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

Iijima

Hamada

Kitamura

et al. 2006

IEICE Electron. Express

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Abstract:The dual supply voltage (dual-V DD ) scheme reduces the active power consumption without performance degradation by using two power supply rails. However, an increase in the delay due to the scaled-down supply voltage has made assigning the lower supply voltage (V DDL ) more difficult in the conventional dual-V DD scheme. We propose a technique for the dual-V DD scheme employing the Active Body-biasing Control (ABC) on PD-SOI, which increases the number of V DDL -cells owing to lowered threshold voltage. Simulation results have shown our approach effectively reduces the power consumption even at low voltage operation.

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Section: Circuit Simulation and Resultsmentioning

confidence: 99%

Section: Dynamic Threshold Voltage Controlmentioning

confidence: 99%

Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

Iijima

Hamada

Kitamura

et al. 2006

IEICE Electron. Express

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“…If this is the case, C will not generate as many new LUT roots as other cuts do when those other cuts do not have this feature. 4 In other words, cut C takes advantage of existing resources and does not require new resources. This reduces the chances that a newly picked cut will cut into the interior territories of existing LUTs.…”

Section: F Cut Selection With Local Cost Adjustmentmentioning

confidence: 99%

“…In [3], a dual supply voltage scaling methodology was designed. The work in [4] introduced variable supply-voltage combined with CVS. It also derived a rule for optimal low Vdd given a high Vdd.…”

mentioning

confidence: 99%

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Chen

Cong

Dong

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. This paper also presents an enhanced clustering algorithm that considers dual supply voltages, honoring the dual-Vdd mapping solution. To carry out various comparisons, we first design a single-Vdd mapping algorithm, named SVmap-2, which achieves a 3.8% total power reduction (15.6% dynamic power reduction) over a previously published low-power mapping algorithm, Emap [11]. We then show that our dual-Vdd mapping algorithm, named DVmap-2, can further improve total power savings by 12.8% over SVmap-2, with a 52.7% dynamic power reduction. Compared to the early single-Vdd version SVmap [14], DVmap-2 is 14.3% better for total power reduction. This is achieved through an ideal selection of the low-Vdd/high-Vdd ratio and the consideration of various voltage changing scenarios during the mapping process.Index Terms-Dual-supply voltages, field-programmable gate array (FPGA), power optimization, technology mapping.

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“…Level converters are obviously not needed for a step-down change in voltage. Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flip flops (see [4] for details.) A polynomial time algorithm for multiple-voltage scheduling of performance-constrained non-pipelined designs is presented by Raje and Sarrafzadeh in [5].…”

Section: Multiple-voltage Designmentioning

confidence: 99%

Low-power RT-level synthesis techniques: a tutorial

Pedram

Abdollahi

2005

IEE Proc., Comput. Digit. Tech.

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-Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. And, while the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to sub-one volt range and further reductions in the supply voltage begin to create more problems than are solved. Under these circumstances, the process of design and the automation tools required to support that process become the critical success factors. In the last decade, huge effort has been invested to come up with a wide range of design solutions that help solve the power dissipation problem for different types of electronic devices, components and systems. These techniques range from RTL power management and multiple voltage assignment, to power-aware logic synthesis and physical design, to memory and bus interface design. This tutorial paper explains a number of representative low power design techniques from this large set. More precisely, we will describe basic techniques, applicable at RT-level and below, that have proven to hold good potential for power optimization in practical design environments.

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A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Cited by 80 publications

References 2 publications

Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

Low-power RT-level synthesis techniques: a tutorial

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