A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

Centurelli, Francesco; Monsurrò, Pietro; Parisi, G.; Tommasino, Pasquale; Trifiletti, Alessandro

doi:10.1109/tcsii.2017.2742240

Cited by 24 publications

(11 citation statements)

References 11 publications

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“…This issue may preclude the use of these topologies for small load capacitors without using techniques such as output lead compensation . A remarkable work is Centurelli et al, where higher FoM values are achieved for a PM of 59° and a low C L = 0.5 pF. However, a much more advanced technology is used (40 nm), and only simulation results are provided.…”

Section: Simulation and Measurement Resultsmentioning

confidence: 99%

“…Hence, low quiescent currents can be used in the differential pair, and at the same time large dynamic currents not bounded by the quiescent currents are generated for large input signals, yielding class AB operation. Several class AB amplifiers have been reported with different adaptive biasing techniques, eg . However, the CF/CA is often unchanged, which may limit the power efficiency and dynamic performance of the OTA.…”

Section: Introductionmentioning

confidence: 99%

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Class AB amplifier with enhanced slew rate and GBW

Garde

López-Martín

Algueta

et al. 2019

Circuit Theory & Apps

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The design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power-efficient adaptive biasing circuit and a class AB current follower using the quasi-floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5-μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small-signal performance.

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Section: Simulation and Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Class AB amplifier with enhanced slew rate and GBW

Garde

López-Martín

Algueta

et al. 2019

Circuit Theory & Apps

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show abstract

“…Over the years, the research community has increasingly focused on reducing the supply voltage and power consumption at the expense of common-mode rejection ratio (CMRR) performance [11][12][13][14]. Several common-mode feedback (CMFB) approaches, which exploit triode-biased devices or current cancellation, have been proposed with the aim of minimizing the common-mode gain in fully differential OTAs, thus improving their CMRR performance [15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

Centurelli

Sala

Monsurrò

et al. 2021

JLPEA

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In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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“…In particular, the reduction in the MOSFET intrinsic gain (g m r d ∼ 10), in the dynamicrange and in the signal-to-noise ratio can severely affect the circuit performance [11][12][13][14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Giustolisi

Palumbo

2021

JLPEA

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In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

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A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

Cited by 24 publications

References 11 publications

Class AB amplifier with enhanced slew rate and GBW

Class AB amplifier with enhanced slew rate and GBW

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

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