A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable Memristive Synapses

Bai, Kangjun; An, Qiyuan; Liu, Lingjia; Yi, Yang

doi:10.1109/tvlsi.2019.2942267

Cited by 32 publications

(7 citation statements)

References 41 publications

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“…The BPNN is trained to detect facial/non-facial features using the resulting PCA. The architectural design of the BPNN is characterized by three strata Feed Forward Neural Network, and supervised learning was employed in BPNN training [28]. The function which activates the hidden layer is referred to as the sigmoid function.…”

Section: Arrangement Via Neural Network (Nn)mentioning

confidence: 99%

Automated Cheating Detection based on Video Surveillance in the Examination Classes

Al_airaji

Aljazaery

Alrikabi

et al. 2022

Int. J. Interact. Mob. Technol.

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A major issue in the field of education is exam malpractice and other forms of academic dishonesty, where efforts made towards the assessment of students are undercut. In order to address this menace, a cheating detection system has been proposed in this study. The system can detect cheating in real-time. The proposed system uses video surveillance to monitor the activities of the student during exams, especially abnormal behavior. The development of the system involved the use of three different techniques, with different functions. The first technique helps in determining the direction of the students’ heads when they move from their initial direction, which is the exam script. Some form of cheating involves students peeping at the exam scripts of other people writing the same exam. Whenever the system observes a deviation that exceeds the set threshold, it classifies the behavior as abnormal. The second technique works with the movement of the student’s iris. It detects when a student’s iris moves in a different direction to copy answers from written documents like mobile phones, books, hands, summary papers. The third technique is used in identifying the contact between a student’s hands and face, as well as that between different students for shared abnormal behavior detection between students, such as sharing of incriminating materials. When any of these is detected, an automatic alarm alerts the authority about the abnormal behavior that has been detected, thereby minimizing the error rate that can occur as a result of manual monitoring.

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Section: Arrangement Via Neural Network (Nn)mentioning

confidence: 99%

Automated Cheating Detection based on Video Surveillance in the Examination Classes

Al_airaji

Aljazaery

Alrikabi

et al. 2022

Int. J. Interact. Mob. Technol.

View full text Add to dashboard Cite

show abstract

“…Artificial DNNs are machine learning algorithms composed of input, hidden, and output layers, designed to emulate the biological neuron network in the brain [ 48 , 49 , 50 ]. To demonstrate the neuromorphic computing capabilities of the proposed MSQ-based EDL synaptic transistors, we trained a multi-layer DNN using the IBM AIHWkit with the handwritten MNIST dataset [ 51 ].…”

Section: Resultsmentioning

confidence: 99%

Organic–Inorganic Hybrid Synaptic Transistors: Methyl-Silsesquioxanes-Based Electric Double Layer for Enhanced Synaptic Functionality and CMOS Compatibility

Hwang,

Park,

Cho

2024

Biomimetics

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Electrical double-layer (EDL) synaptic transistors based on organic materials exhibit low thermal and chemical stability and are thus incompatible with complementary metal oxide semiconductor (CMOS) processes involving high-temperature operations. This paper proposes organic–inorganic hybrid synaptic transistors using methyl silsesquioxane (MSQ) as the electrolyte. MSQ, derived from the combination of inorganic silsesquioxanes and the organic methyl (−CH3) group, exhibits exceptional thermal and chemical stability, thus ensuring compatibility with CMOS processes. We fabricated Al/MSQ electrolyte/Pt capacitors, exhibiting a substantial capacitance of 1.89 µF/cm2 at 10 Hz. MSQ-based EDL synaptic transistors demonstrated various synaptic behaviors, such as excitatory post-synaptic current, paired-pulse facilitation, signal pass filtering, and spike-number-dependent plasticity. Additionally, we validated synaptic functions such as information storage and synapse weight adjustment, simulating brain synaptic operations through potentiation and depression. Notably, these synaptic operations demonstrated stability over five continuous operation cycles. Lastly, we trained a multi-layer artificial deep neural network (DNN) using a handwritten Modified National Institute of Standards and Technology image dataset. The DNN achieved an impressive recognition rate of 92.28%. The prepared MSQ-based EDL synaptic transistors, with excellent thermal/chemical stability, synaptic functionality, and compatibility with CMOS processes, harbor tremendous potential as materials for next-generation artificial synapse components.

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“…BER reduces to 10 −4 reduce RRAM energy by 30 times Bai et al [16] Proposed hybrid structured DNN (hybrid-DNN) combining both spatial and temporal deep learning characteristics.…”

Section: State-of-the-art Hardware Architectures For Feed Forward Dee...mentioning

confidence: 99%

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

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In recent times, the trend in very large scale integration (VLSI) industry is multi-dimensional, e.g. reduction of energy consumption, occupancy of less space, precise result, less power dissipation, faster response etc. To meet these needs, the hardware architecture should be reliable and robust to these problems. Recently, neural network and deep learning has been started to impact the present research paradigm significantly which consists of parameters in the order of millions, nonlinear function for activation, convolutional operation for feature extraction, softmax regression for classification, generative adversarial networks, etc. These operations involve huge calculation and memory overhead. Presently available DSP processors are incapable of performing these operations and they most face the problems e.g. memory overhead, performance drop and compromised accuracy. Moreover, if a huge silicon area is powered to accelerate the operation using parallel computation, the IC's will be having significant chance of burning out due to the considerable generation of heat. Hence, novel dark silicon constraint is developed to reduce the heat dissipation without sacrificing the accuracy. Similarly, different algorithms have been adapted to design a DSP processor compatible for fast performance in neural network, activation function, convolutional neural network and generative adversarial network. In this review, we illustrate the recent developments in hardware for accelerating the efficient implementation of deep learning networks with enhanced performance. The techniques investigated in this review are expected to direct future research challenges of hardware optimization for high-performance computations.

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A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable Memristive Synapses

Cited by 32 publications

References 41 publications

Automated Cheating Detection based on Video Surveillance in the Examination Classes

Automated Cheating Detection based on Video Surveillance in the Examination Classes

Organic–Inorganic Hybrid Synaptic Transistors: Methyl-Silsesquioxanes-Based Electric Double Layer for Enhanced Synaptic Functionality and CMOS Compatibility

From DNNs to GANs: Review of efficient hardware architectures for deep learning

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