A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique

Chakraborty, Raj; Lamech, Charles; Acharyya, Dhruva; Plusquellic, Jim

doi:10.1145/2463209.2488806

Cited by 9 publications

(11 citation statements)

References 5 publications

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“…The source of random information varies widely among proposed PUF architectures, and includes transistor threshold voltages [4], delay chains and ring oscillators (RO) [2][3][4][5][6], FPGAs [7,8], SRAMs [9], leakage current [10], metal resistance [11], transistor transconductance [12], the path delays of core logic macros [13][14][15], memristors [16], scan chains [17], phase change memory [18], plus many others.…”

Section: Related Workmentioning

confidence: 99%

Analysis of Entropy in a Hardware-Embedded Delay PUF

et al. 2017

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Abstract:The magnitude of the information content associated with a particular implementation of a Physical Unclonable Function (PUF) is critically important for security and trust in emerging Internet of Things (IoT) applications. Authentication, in particular, requires the PUF to produce a very large number of challenge-response-pairs (CRPs) and, of even greater importance, requires the PUF to be resistant to adversarial attacks that attempt to model and clone the PUF (model-building attacks). Entropy is critically important to the model-building resistance of the PUF. A variety of metrics have been proposed for reporting Entropy, each measuring the randomness of information embedded within PUF-generated bitstrings. In this paper, we report the Entropy, MinEntropy, conditional MinEntropy, Interchip hamming distance and National Institute of Standards and Technology (NIST) statistical test results using bitstrings generated by a Hardware-Embedded Delay PUF called HELP. The bitstrings are generated from data collected in hardware experiments on 500 copies of HELP implemented on a set of Xilinx Zynq 7020 SoC Field Programmable Gate Arrays (FPGAs) subjected to industrial-level temperature and voltage conditions. Special test cases are constructed which purposely create worst case correlations for bitstring generation. Our results show that the processes proposed within HELP to generate bitstrings add significantly to their Entropy, and show that classical re-use of PUF components, e.g., path delays, does not result in large Entropy losses commonly reported for other PUF architectures.

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Section: Related Workmentioning

confidence: 99%

Analysis of Entropy in a Hardware-Embedded Delay PUF

et al. 2017

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“…The introduction of the silicon PUF as a mechanism to generate random bitstrings began in [1], although their use as chip identifiers began a couple years earlier [2]. Since their introduction, there have been many proposed architectures that are promising for PUF implementations, including those that leverage variations in transistor threshold voltages [2][3], in delay chains and ROs [1][4-7+many others], in SRAMs [8][9], in leakage current [10], in metal and transistor resistance [11][12], in clock networks [13], in scan chains [14] and transmission lines [15] …”

Section: Related Workmentioning

confidence: 99%

“…In addition to the Normalization technique described above, the PUF Engine also implements a method called XMR for increasing the probability of correctly regenerating the bitstring [12]. XMR creates an odd number of 'copies' of the bitstring during enrollment and regeneration.…”

Section: Reliability Enhancing Techniquesmentioning

confidence: 99%

“…• An entropy source that leverages single vias, minimum width metal and polysilicon wires over 5 of the metal layers available in the IP block. References [11][12] describe preliminary results from a test chip which uses a metal-based entropy source, a 'pulseshrinking' version of the VDC as well as processes related to calibration, thresholding and XMR. However, this paper integrates all of these components in a unified system architecture and investigates each of the novel concepts described above.…”

Section: Introductionmentioning

confidence: 99%

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IP-level implementation of a resistance-based physical unclonable function

Ismari

Plusquellic

2014

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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A complete on-chip implementation of a bit generation engine using a physical unclonable function is presented in this paper. The bit generation engine, called the JellyFishPUF (JFP), provides keying material for encryption, authentication bitstrings for anti-counterfeiting and true random number generation. JFP utilizes a Physical Unclonable Function that is based on resistance variations in metals and transistors. JFP is fully implemented as a layout in an area of 0.125 mm 2 using a 65 nm technology, which includes a 2KB SRAM for public data storage. The bitstrings produced from Monte Carlo SPICE-level simulations of the entropy source in combination with logic simulations of the digital engine are evaluated with respect to randomness, uniqueness and stability metrics across a wide range of temperature and voltage corners.

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“…The error correction information is stored in reliable, digital storage, e.g., in an onchip NVM or an off-chip storage device. A second thresholding-based technique 'avoids' bit flips by being selective regarding which components of the entropy source can be compared reliably to generate a bit [6]. However, thresholding techniques also require helper data that indicate which comparisons are reliable.…”

Section: Introductionmentioning

confidence: 99%

A non-volatile memory based physically unclonable function without helper data

Che¹,

Plusquellic²,

Bhunia³

2014

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Stability across environmental variations such as temperature and voltage, is critically important for Physically Unclonable Functions (PUFs). Nearly all existing PUF systems to date need a mechanism to deal with "bit flips" when exact regeneration of the bitstring is required, e.g., for cryptographic applications. Error correction (ECC) and error avoidance schemes have been proposed but both of these require helper data to be stored for the regeneration process. Unfortunately, helper data adds time and area overhead to the PUF system and provides opportunities for adversaries to reverse engineer the secret bitstring. In this paper, we propose a non-volatile memorybased (NVM) PUF that is able to avoid bit flips without requiring any type of helper data. A voltage-to-digital converter technique is described for digitizing the analog entropy source and a robust median-finding algorithm is proposed as the reprograming strategy. Analysis on published experimental data is presented to demonstrate the practicability of our proposed strategy. We describe the technique in the context of emerging nano-devices, in particular, resistive random access memory (Memristor) cells, but the methodology is applicable to any type of NVM including Flash.

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A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique

Cited by 9 publications

References 5 publications

Analysis of Entropy in a Hardware-Embedded Delay PUF

Analysis of Entropy in a Hardware-Embedded Delay PUF

IP-level implementation of a resistance-based physical unclonable function

A non-volatile memory based physically unclonable function without helper data

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