A transport-layer network for distributed FPGA platforms

Jun, Sang-Woo; Liu, Ming; Xu, Shuotao; Arvind, .

doi:10.1109/fpl.2015.7293976

Cited by 13 publications

(7 citation statements)

References 10 publications

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“…In the past, FPGAs were typically connected through pointto-point serial links with fixed topologies and with lightweight or proprietary protocols [1], [31]- [34]. Many of these implementations build on top of low-level networking IP cores provided by Xilinx and Intel, such as the Ethernet Media Access Controller (MAC) [13], [14], [35].…”

Section: Related Workmentioning

confidence: 99%

EasyNet: 100 Gbps Network for HLS

Korolija

Alonso

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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The massive deployment of FPGAs in data centers is opening up new opportunities for accelerating distributed applications. However, developing a distributed FPGA application remains difficult for two reasons. First, commonly available development frameworks (e.g., Xilinx Vitis) lack explicit support for networking. Developers are, thus, forced to build their own infrastructure to handle the data movement between the host, the FPGA, and the network. Second, distributed applications are made even more complex by using low level interfaces to access the network and process packets. Ideally, one needs to combine high performance with a simple interface for both point-to-point and collective operations. To overcome these inefficiencies and enable further research in networking and distributed application on FPGAs, we first show how to integrate an open-source 100 Gbps TCP/IP stack into a state-of-the-art FPGA development framework (Xilinx Vitis) without degrading its performance. Further, we provide a set of MPI-like communication primitives for both point-to-point and collective operations as a High Level Synthesis (HLS) library. Our point-to-point primitives saturate a 100 Gbps link and our collective primitives achieve low latency. With our approach, developers can write hardware kernels in high level languages with the network abstracted away behind standard interfaces. To evaluate the ease of use and performance in a real application, we distribute a K-Means algorithm with the new stack and achieve a 1.9X and 3.5X throughput increase with 2 FPGAs and 4 FPGAs respectively.

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Section: Related Workmentioning

confidence: 99%

EasyNet: 100 Gbps Network for HLS

Korolija

Alonso

2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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“…Work has been done exploring efficient DNN inference on FPGAs, both on a single node and on FPGA clusters [13], [14]. Most of the approaches use FPGA clusters connected with point-to-point serial links and proprietary protocols [8], [15]- [17], where the cost to build such a cluster is high and the flexibility of the deployment is limited as the topology is fixed. In contrast, we focus on FPGA clusters embedded on the network data path and connected with the rest of the data center infrastructure (e.g., high bandwidth links and network switches), as indicated by Microsoft Brainwave [18], [19].…”

Section: Acceleration With Fpga Clustersmentioning

confidence: 99%

Distributed Recommendation Inference on FPGA Clusters

Zhu

Jiang

et al. 2021

2021 31st International Conference on Field-Programmable Logic and Applications (FPL)

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Deep neural networks are widely used in personalized recommendation systems. Such models involve two major components: the memory-bound embedding layer and the computation-bound fully-connected layers. Existing solutions are either slow on both stages or only optimize one of them. To implement recommendation inference efficiently in the context of a real deployment, we design and implement an FPGA cluster optimizing the performance of both stages. To remove the memory bottleneck, we take advantage of the High-Bandwidth Memory (HBM) available on the latest FPGAs for highly concurrent embedding table lookups. To match the required DNN computation throughput, we partition the workload across multiple FPGAs interconnected via a 100 Gbps TCP/IP network. Compared to an optimized CPU baseline (16 vCPU, AVX2-enabled) and a one-node FPGA implementation, our system (four-node version) achieves 28.95× and 7.68× speedup in terms of throughput respectively. The proposed system also guarantees a latency of tens of microseconds per single inference, significantly better than CPU and GPU-based systems which take at least milliseconds.

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“…A customized protocol, BlueLink [16] using high-speed serial links, showed better area-performance characteristics than existing network protocols for their custom computing requirements. Jun et al [17] presented a parameterized, low overhead transport layer network with virtual channels and end-to-end flow control for distributed FPGA applications. Their prototype cluster is made up of 20 Xilinx VC707 FPGA boards connected through their high-speed serial links.…”

Section: Related Workmentioning

confidence: 99%

“…In addition, we added a credit-based flow control mechanism [18] for backpressure propagation between FPGAs. Unlike in [17], however, careful analysis based on the physical constraints is done for the communication buffer requirements, which will be discussed in detail within the next section. We selected the credit-based scheme due to the advantages presented in [19], [20] such as: it is faster than its rate-based counterparts; there is no data loss if there is any congestion; and data rate can be as high as the full link speed with no data loss, which promises good network resource utilization.…”

Section: Related Workmentioning

confidence: 99%

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

Mondigo

Ueno

Sano

et al. 2019

IEICE Trans. Inf. & Syst.

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Since the hardware resource of a single FPGA is limited, one idea to scale the performance of FPGA-based HPC applications is to expand the design space with multiple FPGAs. This paper presents a scalable architecture of a deeply pipelined stream computing platform, where available parallelism and inter-FPGA link characteristics are investigated to achieve a scaled performance. For a practical exploration of this vast design space, a performance model is presented and verified with the evaluation of a tsunami simulation application implemented on Intel Arria 10 FPGAs. Finally, scalability analysis is performed, where speedup is achieved when increasing the computing pipeline over multiple FPGAs while maintaining the problem size of computation. Performance is scaled with multiple FP-GAs; however, performance degradation occurs with insufficient available bandwidth and large pipeline overhead brought by inadequate data stream size. Tsunami simulation results show that the highest scaled performance for 8 cascaded Arria 10 FPGAs is achieved with a single pipeline of 5 stream processing elements (SPEs), which obtained a scaled performance of 2.5 TFlops and a parallel efficiency of 98%, indicating the strong scalability of the multi-FPGA stream computing platform.

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A transport-layer network for distributed FPGA platforms

Cited by 13 publications

References 10 publications

EasyNet: 100 Gbps Network for HLS

EasyNet: 100 Gbps Network for HLS

Distributed Recommendation Inference on FPGA Clusters

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs

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