A tri-loop low-dropout regulator with fast transient response based on flipped voltage follower

Abstract

This paper introduces a low-dropout regulator (LDO) with a quick transient response to the load and no off-chip capacitance. The LDO in this work powers digital modules in system-on-chip (SoC). It has low output voltage variation and fast recovery time during load changes. This paper proposed a novel tri-loop regulation method. The basic loop is a conventional feedback loop for LDO to ensure output voltage accuracy. The transient-enhanced loop is an improved design based on the flipped voltage follower (FVF) that compensates for the effect of removing off-chip capacitance on circuit stability. The introduced Miller capacitor is used to form the AC-coupled loop, further ensuring pole separation. It is worth mentioning that this paper introduces 2 FVFs for building basic loop and transient-enhanced loop. In addition, a bandgap reference (BGR) with a self-starting circuit is designed in this paper. The LDO described in this paper operates at 5V. The LDO is based on a 0.18 um CMOS process. The dropping and rising voltages are merely 24.5 mV and 25 mV when the load current (I ) fluctuates between 1 and 50 mA. And the corresponding settling times are 2.5 us and 1.9 us respectively. The LDO described in this paper has an output of 1.8 V and the load regulation (LDR) is as low as 6.68 uV/mA.