A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications

Iturbe, Xabier; Venu, Balaji; Özer, Emre; Das, Shidhartha

doi:10.1109/dsn-w.2016.57

Cited by 50 publications

(55 citation statements)

References 4 publications

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“…This greatly reduces the recovery time when compared to DMR. In the unlikely event that two or more processors encounter an error such that all three processors disagree, TMR restores all three processors to a previous Save/Restore Point in the same way as DMR: the voter contains a hardware implemented finite state machine to create the Save/Restore Point and recover from errors [7][8][9][10][11][12][13]. The voter is typically assumed to be immune to errors or is hardened in some way.…”

Section: Hardware Redundancymentioning

confidence: 99%

Adaptive-Hybrid Redundancy with Error Injection

et al. 2019

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Adaptive-Hybrid Redundancy (AHR) shows promise as a method to allow flexibility when selecting between processing speed and energy efficiency while maintaining a level of error mitigation in space radiation environments. Whereas previous work demonstrated AHR’s feasibility in an error free environment, this work analyzes AHR performance in the presence of errors. Errors are deliberately injected into AHR at specific times in the processing chain to demonstrate best and worst case performance impacts. This analysis demonstrates that AHR provides flexibility in processing speed and energy efficiency in the presence of errors.

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Section: Hardware Redundancymentioning

confidence: 99%

Adaptive-Hybrid Redundancy with Error Injection

et al. 2019

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“…Rapidly increasing core counts for workloads such as HPC mean there are more points of failure in systems, and therefore a higher chance of hard faults [5], [6], [7]. Increased variance in chips at lower source voltages [17], [19] make timing violations more common, and the unfavorable conditions many safety critical systems operate in, such as those in space or the automotive industry [2], [3], [9], also serve to increase the number of faults observed in modern systems. Running cores in lockstep, or running the same code twice on the same core via multi-threading, come with significant space and time overheads, respectively.…”

Section: A Faultsmentioning

confidence: 99%

“…At the same time, the tolerance of many workloads to the occurrence of errors has reduced. For example, strict safety standards, along with suboptimal environmental conditions, require error detection hardware within CPUs used for automotive, health, nuclear power and machinery applications [2], [3], [4]. Space applications require reliability for economic reasons [3], and large scale HPC systems require reliability due to having a large number of potential failures [5], [6], [7].…”

Section: Introductionmentioning

confidence: 99%

“…Certain industries mandate stringent safety standards to achieve certification, such as automotive, where redundancy is required for ASIL-C and ASIL-D ratings [8]. The current industry approach to address this is hardware lock-step error detection [3], [9], [10]. This involves running multiple copies of a program on separate, synchronised CPUs, and comparing the results in hardware.…”

Section: Introductionmentioning

confidence: 99%

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Parallel Error Detection Using Heterogeneous Cores

Ainsworth

Jones

2018

2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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Microprocessor error detection is increasingly important, as the number of transistors in modern systems heightens their vulnerability. In addition, many modern workloads in domains such as the automotive and health industries are increasingly error intolerant, due to strict safety standards. However, current detection techniques require duplication of all hardware structures, causing a considerable increase in power consumption and chip area. Solutions in the literature involve running the code multiple times on the same hardware, which reduces performance significantly and cannot capture all errors. We have designed a novel hardware-only solution for error detection, that exploits parallelism in checking code which may not exist in the original execution. We pair a high-performance out-of-order core with a set of small low-power cores, each of which checks a portion of the out-of-order core's execution. Our system enables the detection of both hard and soft errors, with low area, power and performance overheads.

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“…Hardware voting today is used exclusively for protecting simpler FT processor cores at the microcontroller level [4], [15], and for accelerators [16] supporting application code with tightly constrained program structure. Hence, the application of this hardware-centered approach has become a technical deadend for protecting widely used application processor designs intended for general-purpose computing, while accelerators by themselves would only assure FT for computation and data offloaded to such a device.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Fault Tolerance Through Resource Pooling

Fuchs

Murillo

Plaat

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Miniaturized satellites are currently not considered suitable for critical, high-priority, and complex multi-phased missions, due to their low reliability. As hardware-side fault tolerance (FT) solutions designed for larger spacecraft can not be adopted aboard very small satellites due to budget, energy, and size constraints, we developed a hybrid FT-approach based upon only COTS components, commodity processor cores, library IP, and standard software. This approach facilitates fault detection, isolation, and recovery in software, and utilizes fault-coverage techniques across the embedded stack within a multiprocessor system-on-chip (MPSoC). This allows our FPGA-based proofof-concept implementation to deliver strong fault-coverage even for missions with a long duration, but also to adapt to varying performance requirements during the mission. The operator of a spacecraft utilizing this approach can define performance profiles, which allow an on-board computer (OBC) to trade between processing capacity, fault coverage, and energy consumption using simple heuristics. The software-side FT approach developed also offers advantages if deployed aboard larger spacecraft through spare resource pooling, enabling an OBC to more efficiently handle permanent faults. This FT approach in part mimics a critical biological system's ability to tolerate faults, adapt to permanent failure, and enables graceful aging of an MPSoC.

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A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications

Cited by 50 publications

References 4 publications

Adaptive-Hybrid Redundancy with Error Injection

Adaptive-Hybrid Redundancy with Error Injection

Parallel Error Detection Using Heterogeneous Cores

Dynamic Fault Tolerance Through Resource Pooling

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