A true single-phase-clock dynamic CMOS circuit technique

Ji-Ren, Y.; Karlsson, Ingrid; Svensson, Christer

doi:10.1109/jssc.1987.1052831

Cited by 182 publications

(39 citation statements)

References 3 publications

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“…In this section TSPC [3], [9], and E-TSPC [10] based flipflops are analysed with its power consumption and frequency response.In dynamic latch frequency synthesiser, multiple phase clock frequency synthesiser are better for compact circuits and these are more power efficient than single phase frequency synthesizer. The maximum operating frequency is also higher.…”

Section: Analysis Of Tspc Ande-tspc Flip-flopmentioning

confidence: 99%

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Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

Kumar¹,

Kapoor²

2017

International Journal of Advanced Research in Computer and Comm

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Abstract:In this paper a high operating frequency and power efficient TSPC prescaler layout is proposed and compared with the existing TSPC and E-TSPC prescalers on the basis of operating frequency and power consumption. The maximum operating frequency of the proposedTSPC prescaler is 7.2 GHz which is 10% higher than other TSPC based prescalers and 7% than E-TSPC based prescalers with average power consumption of 307 µW at 1.8 V supply voltage. This High Frequency is achieved by reducing propagation delay in PMOS and NMOS at different stages. The power consumption in divide by 2 and divide by 3 mode is 3% to 10% better than all other prescalers and four times better than those prescalers which can be operated higher than 6.5 GHz frequency.This prescaler consumes 348µW in divide by 2 mode and 244µW in divide by 3 mode.

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Section: Analysis Of Tspc Ande-tspc Flip-flopmentioning

confidence: 99%

“…Basically prescaler are made of D flop-flop and logic gates. Those D flop-flopscan be driven by single phase clock [3], [5] or multiple phase clock. Those logic gates are used between D flop-flops to generate two consecutive divisional ratios.…”

Section: Introductionmentioning

confidence: 99%

Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

Kumar¹,

Kapoor²

2017

International Journal of Advanced Research in Computer and Comm

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“…The E-TSPC 2/3 pre scaler consumes large short circuit power and has a higher frequency of operation than that of [5].Wideband single phase clock 2/3 prescaler Here, the transistors M2, M25,M4,Ms in DFFI helps to eliminate the short-circuit power during the divide-by-2 operation. The switching of division ratios between 2 and 3 is controlled by logic signal MC.…”

Section: Proposed Systemmentioning

confidence: 99%

Design of a Low Power Clock Multi Band Network for Supplying the Multi Clock Domain Networks

Indraja¹,

Harmya²,

Lakshmi³

et al. 2014

International Journal of Advanced Research in Computer and Comm

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when working with IC's most of the power will be consumed for making the IC in to active working state. This depends on the clock distribution networks. Because the clock signals have the high switching activity. Normally for a multi clock domain networks the power consumed by the clock signals is too high to lower this we generally use multiple PLL's, in this project we aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This design is highly useful for communication applications. A low power clock model network is designed for LAN using pulse-swallow topology and the design is modelled using Verilog simulated using Model sim and implemented in Xilinx.

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“…Flip-flops are required to cover a wide operational frequency range, which includes a standby mode for mobile applications. Among many flip-flop architectures, a true single-phase clocked (TSPC) flip-flop, which consists of a dynamic circuit, has been utilized for high speed-operation [1,2]. A TSPC flip-flop has a small area and a low clock power.…”

Section: Introductionmentioning

confidence: 99%

A true single-phase clocked flip-flop with leakage current compensation

Lee

Jang

2012

IEICE Electron. Express

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A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65 nm CMOS process with a 1 V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2 GHz, exhibits an error-free operation at low operational frequencies such as 1 MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.

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A true single-phase-clock dynamic CMOS circuit technique

Cited by 182 publications

References 3 publications

Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

Design of a Low Power Clock Multi Band Network for Supplying the Multi Clock Domain Networks

A true single-phase clocked flip-flop with leakage current compensation

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