A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders, Frank; Bekooij, Marco; Corporaal, Henk

doi:10.1145/1629435.1629488

Cited by 6 publications

(4 citation statements)

References 20 publications

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“…MJPEG) and (iv) the proposed Pthreads approach was evaluated in a real NoC-based MPSoC that has already been prototyped in different FPGAs and also ported to ASIC to evaluate the area overhead, while Marangiu's approach uses a simulator to validate his idea. Ophelders [6] proposes a software cache coherence protocol that was validated on a dual-core ARM9 architecture using the SPLASH2 benchmark. Ophelders work differs from ours in two aspects.…”

Section: Related Workmentioning

confidence: 99%

Simultaneous multithreading support in embedded distributed memory MPSoCs

Garibotti

Ost

Busseuil

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Scalability and programmability are important issues in large homogeneous MPSoCs. Such architectures often rely on explicit message-passing among processors, each of which possessing a local private memory. This paper presents a low-overhead hardware/software distributed shared memory approach that makes such architectures multithreading-capable. The proposed solution is implemented into an open-source message-passing MPSoC through developing a POSIX-like thread API, which shows excellent scalability using application kernels used for benchmarking in shared-memory systems. This approach efficiently draws strengths from the on-chip distributed private memory that opens the way to exposing the multithreading programmability/capabilities of that component as a generalpurpose accelerator.

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Section: Related Workmentioning

confidence: 99%

Simultaneous multithreading support in embedded distributed memory MPSoCs

Garibotti

Ost

Busseuil

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…To preserve coherency of the shared memory, software cache coherency has to be implemented. The main advantage of software cache coherency is the fact that the programmer has a global view of the system, and so can optimize the protocol of synchronization depending on the nodes possessing the data [54]: knowing the owner of the data and the order of read/write operations on it allows more precise flush/invalidate actions in the caches. However, software cache coherency implies a higher performance penalty for the computation of the synchronization protocols.…”

Section: A Hybrid Memory Modelmentioning

confidence: 99%

Adaptation Strategies in Multiprocessors System on Chip

Busseuil

Almeida

Ost

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Multi-processor System-on-Chips (MPSoCs) have become increasingly popular over the past decade. They permit balancing performance and flexibility, the latter being a key feature that makes possible reusing the same silicon across several product lines or even generations. This popularity makes highlight on new challenges to deal with the increasing complexity of such systems. Programmability issues, for example, are considered with a lot of attention, as those architectures allow new dimensions in design exploration. In this context, the development of adaptable mechanisms permits the optimization of the system behavior. This chapter explors three different adaptable mechanisms, and shows their benefits : frequency scaling, task migration techniques and memory organization. The modification of the frequency of each processor of a multi-core system allows fine tuning of power consumption under a varying process workload. Task migration permits balancing load among the several processors the system is made of. Our long-term vision of future embedded devices lies in adaptive systems made of thousands of processors in which tasks frequently migrate in response to the system state that is continuously monitored. Memory organization is a crucial criterion in MPSoC performance optimization, as memory access latency of remote data increases exponentially with respect to the number of cores. The computation-based programming model commonly used in single-core or few-cores based systems are no more suitable, and a transaction-based model are necessary to reach performances needs of new multimedia application.

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“…Hardware cache coherency or RMW instructions are not always applied in embedded systems, because of high hardware costs and the lack of IP [5]. Additionally, hardware cache coherency is unsupported for FPGA targets by common system-on-chip (SoC) design tools, such as Xilinx XPS and Altera SOPC Builder, as neither the MicroBlaze nor the Nios II support it.…”

Section: Introductionmentioning

confidence: 99%

An efficient asymmetric distributed lock for embedded multiprocessor systems

Rutgers

Bekooij

Smit

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Efficient synchronization is a key concern in an embedded many-core system-on-chip (SoC). The use of atomic read-modify-write instructions combined with cache coherency as synchronization primitive is not always an option for sharedmemory SoCs due to the lack of suitable IP. Furthermore, there are doubts about the scalability of hardware cache coherency protocols. Existing distributed locks for NUMA multiprocessor systems do not rely on cache coherency and are more scalable, but exchange many messages per lock.This paper introduces an asymmetric distributed lock algorithm for shared-memory embedded multiprocessor systems without hardware cache coherency. Messages are exchanged via a low-cost inter-processor communication ring in combination with a small local memory per processor. Typically, a mutex is used over and over again by the same process, which is exploited by our algorithm. As a result, the number of messages exchanged per lock is significantly reduced. Experiments with our 32-core system show that when having locks in SDRAM, 35% of the memory traffic is lock related. In comparison, our solution eliminates all of this traffic and reduces the execution time by up to 89%.

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A tuneable software cache coherence protocol for heterogeneous MPSoCs

Cited by 6 publications

References 20 publications

Simultaneous multithreading support in embedded distributed memory MPSoCs

Simultaneous multithreading support in embedded distributed memory MPSoCs

Adaptation Strategies in Multiprocessors System on Chip

An efficient asymmetric distributed lock for embedded multiprocessor systems

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