A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

Li, Cong; Zhang, Yiqi; Li, Zhang; Jin, Gang

doi:10.1088/1674-1056/23/3/038502

Cited by 11 publications

(4 citation statements)

References 21 publications

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“…Scaled down into nanometers, conventional Si MOSFETs are facing the problems of forming ultra-steep doping profile in p-n junctions, [1][2][3][4] and field-effect transistors (FETs) without junctions, i.e., junctionless FETs (JLFETs) were proposed to eliminate the stringent requirement. [5][6][7][8][9][10] Unlike "regular" p-n junction-based FET, the JLFET usually has the same uniform doping concentration in the source, channel and drain region.…”

Section: Introductionmentioning

confidence: 99%

Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect*

Wang¹,

Shi²,

Zhang³

et al. 2021

Chinese Phys. B

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A novel n-type junctionless field-effect transistor (JLFET) with a step-gate-oxide (SGO) structure is proposed to suppress the gate-induced drain leakage (GIDL) effect and off-state current I off. Introducing a 6-nm-thick tunnel-gate-oxide and maintaining 3-nm-thick control-gate-oxide, lateral band-to-band tunneling (L-BTBT) width is enlarged and its tunneling probability is reduced at the channel--drain surface, leading the off-state current I off to decrease finally. Also, the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET, which could alleviate the capacitive load of the transistor in the circuit applications. Sentaurus simulation shows that I off of the new optimized JLFET reduced significantly with little impaction on its on-state current I on and threshold voltage V TH becoming less, thus showing an improved I on/I off ratio (5 × 104) and subthreshold swing (84 mV/dec), compared with the scenario of the normal JLFET. The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail, which could provide useful instruction for the device design.

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Section: Introductionmentioning

confidence: 99%

Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect*

Wang¹,

Shi²,

Zhang³

et al. 2021

Chinese Phys. B

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show abstract

“…[4,5] To overcome this limitation, various alternative devices are being proposed, and a new class of field effect device called the junctionless field-effect transistor (JLFET) has attract lots of research attention in recent years. [6][7][8][9][10][11][12][13][14] The basic structure of a JLFET consists of a uniformly highly doped silicon channel controlled by at least an on gate electrode. Unlike "regular" junction-based FETs, in JLFET, both the source and the drain have the same type of doping as the channel, and there is no pn junction.…”

Section: Introductionmentioning

confidence: 99%

Enhancement of off-state characteristics in junctionless field effect transistor using a field plate

Wang

Zhang

et al. 2018

Chinese Phys. B

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In this paper, a novel junctionless field effect transistor (JLFET) is proposed. In the presence of a field plate between gate and drain, the gate-induced drain leakage (GIDL) effect is suppressed due to the decrease of lateral band-to-band tunneling probability. Thus, the off-state current I off , which is mainly provided by the GIDL current, is reduced. Sentaurus simulation shows that the I off of the new optimized JLFET is reduced by ∼ 2 orders and its sub-threshold swing can reach 76.8 mV/decade with little influence on its on-state current I on , so its I on /I off ratio is improved by 2 orders of magnitude compared with that of the normal JLFET. Optimization of device parameters such as Φ fps (the work difference between field plate and substrate) and L FP (the length of field plate), is also discussed in detail.

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“…Moreover, drain‐induced barrier lowering (DIBL), one of the typical short‐channel effects, becomes more and more severe with the decrease of channel length . To overcome these problems, a dual‐material gate (DMG) structure has been proposed and applied to improve the performance of JL MOSFET . Recently, a novel structure called junctionless dual‐material double‐gate (JLDMDG) MOSFET has been proposed, and its electrical characteristic has been investigated by using three‐dimensional (3D) numerical simulations .…”

Section: Introductionmentioning

confidence: 99%

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

Wang

Zhang

et al. 2015

Int J Numerical Modelling

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SUMMARYOn the basis of quasi-two-dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual-material double-gate (JLDMDG) metal-oxide-semiconductor field-effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single-material double-gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll-off, drain-induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three-dimensional numerical device simulator ISE.

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A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

Cited by 11 publications

References 21 publications

Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect*

Device physics and design of FD-SOI JLFET with step-gate-oxide structure to suppress GIDL effect*

Enhancement of off-state characteristics in junctionless field effect transistor using a field plate

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

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