A two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM

Abstract

Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. In this paper a structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti,iA1(2S%Cu)/Si metal lines patterned by RIE. This structure has been successfully implemented on both BEOL test sites and in device runs to fabricate a selectively scaled 0Spm channel length 64Kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal or better than that achieved with metal lift-off processing. Functional testing of the 64Kb S R A M produced many chips with better than 90% yield, also equal or better than that achieved with a non-planarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2.N o degradation of device characteristics due to the BEOL processing could be detected.

Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects

“…In addition, we find that at any given concentration of chemicals, polish rates increase as a function of increasing temperature of the slurry. By controlling the temperature of the recirculating water which flows through the polish table the temperature of the slurry con-This process can readily be applied to form W vias in an SiO~ insulator layer (6,7). A typical process sequence involves deposition of the insulator layer followed by lithographic patterning of the insulator, sequential deposition of both an adhesion layer and blanket W, followed by polishing to remove the surface W. Figure 6 is a scanning electron micrograph top down view of W patterns that result after processing.…”

“…Fully planarized, two level interconnect structures, with W studs forming the contacts to the underlying Si device areas and between the wiring levels i.e. (W studl M1-W stud2-M2), have been recently fabricated (6,7). The W stud levels were formed in a chemical-mechanical polish process using the K-F-En process chemistry.…”

“…The presence of a minimum in the mobility vs. doping concentration diagram was explained in terms of carrier trapping at grain boundaries (grain boundary trapping model) (3,4). It has been reported that the microstructure of polysilicon films depends on the deposition and annealing temperatures (5), dopant concentration (6), and film thickness (7).…”

“…tered Ti/TiN adhesion layer, W was deposited using an LPCVD process (11,12) in a batch CVD reactor (Genus 8402). Patterned wafers (6) for demonstration of the recessed W chemical-mechanical polishing process were prepared either by the Yorktown or East Fishki]l Si Facility. These wafers had W deposited into RIE patterned features of a planarized SiO2, with the planarization achieved using a previously described (10) chemical-mechanical polish process to smooth topographic variations in the SiQ insulator.…”

“…Given the nature of the polish mechanism described, we suggest that the particular etchant-passivator combination discussed here is not the only chemical system that could be used for successful fabrication of interconnect structures. Preliminary descriptions of the application of this technology to form a fully planarized interconnect structure with 1.2 ~tm contacts, as applied to a 64 Kb complimentary metal oxide semiconductor static random access memory (CMOS SRAM), and, using x-ray lithography to achieve 0.5 #m on all interconnect levels, have previously appeared (6,7).…”