A Two-Mask Process for Fabrication of Bottom-Gate IGZO-Based TFTs

Uhm, Hyun‐Seok; Lee, Sanghyuk; Kim, Won; Park, Jin-Seok

doi:10.1109/led.2012.2182986

Cited by 16 publications

(7 citation statements)

References 8 publications

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“…The overlapping region was clearly observable among the devices fabricated using the traditional four-photo-mask process in Figure 3 c, which yielded parasitic capacitance between S/D and gate electrodes ( C gd , C gs ). The parasitic capacitance was proportional to the area of overlapping region ( W × L ov ), yielding increased feed-through voltage, noise, and circuit delay in devices typically used in displays applications [ 12 ].…”

Section: Resultsmentioning

confidence: 99%

“…However, four or five-photo-masks were used during fabrication. To reduce the fabrication costs and prevent hydrogen-based material from affecting the a-IGZO active layer during ES deposition [ 11 ], Uhm et al proposed a two-photo-mask scheme that employed a gray-tone photomask to fabricate TFT devices [ 12 ]; however, the lack of an ES layer can cause damage to the a-IGZO active island when etching the S/D electrodes. In addition, the ZnO TFT with three photomasks was also proposed [ 13 ].…”

Section: Introductionmentioning

confidence: 99%

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A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Fan

Shang

et al. 2014

Materials

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Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm 2 /V· s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased. OPEN ACCESSMaterials 2014, 7 5762

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Fan

Shang

et al. 2014

Materials

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“…In general, a-IGZO TFTs applied in active-matrix liquid-crystal displays and active-matrix organic light-emitting diodes are typically fabricated using a back-channel-etching structure and five photomasks. To reduce the fabrication cost, Uhm et al proposed a two-photomask scheme in which a gray-tone photomask was used to fabricate TFT devices [ 8 ]; however, the lack of an etching-stop (ES) layer damages the a-IGZO active island when source/drain (S/D) electrodes are etched. In a typical process, an additional photomask step is required for creating an ES pattern, presenting a trade-off between fabrication cost and device stability.…”

Section: Introductionmentioning

confidence: 99%

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process

Fan

Shang

et al. 2015

Materials

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This study proposes a two-photomask process for fabricating amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) that exhibit a self-aligned structure. The fabricated TFTs, which lack etching-stop (ES) layers, have undamaged a-IGZO active layers that facilitate superior performance. In addition, we demonstrate a bilayer passivation method that uses a polytetrafluoroethylene (Teflon) and SiO2 combination layer for improving the electrical reliability of the fabricated TFTs. Teflon was deposited as a buffer layer through thermal evaporation. The Teflon layer exhibited favorable compatibility with the underlying IGZO channel layer and effectively protected the a-IGZO TFTs from plasma damage during SiO2 deposition, resulting in a negligible initial performance drop in the a-IGZO TFTs. Compared with passivation-free a-IGZO TFTs, passivated TFTs exhibited superior stability even after 168 h of aging under ambient air at 95% relative humidity.

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“…[1][2][3] Recently, the new TFTs with transparent oxide semiconductors have attracted much attention as potential candidates, due to their unique optical and electrical advantages as compared to conventional Si TFTs, such as high mobility, low cost, excellent uniformity, and good transparency to visible light. Particularly, indium gallium zinc oxide (IGZO) TFT [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] with superior stability and performance is one of the most promising candidates and has been widely studied. Moreover, the IGZO TFTs can be processed with very low thermal budget and used in emerging flexible display applications.…”

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confidence: 99%

Low Operation Voltage InGaZnO Thin Film Transistors with LaAlO₃Gate Dielectric Incorporation

Zheng

Cheng

Chen

2013

ECS J. Solid State Sci. Technol.

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In this paper, we report low operation voltage indium gallium zinc oxide (IGZO) thin film transistors (TFTs) incorporating a high-κ lanthanum aluminum oxide (LaAlO 3 ) as gate dielectric. Good TFT characteristics were achieved simultaneously, including a small subthreshold swing (SS) of 98 mV/dec, a low threshold voltage (V t ) of 0.29 V, a good on-off-state drive current ratio (I on /I off ) of 1.1 × 10 5 , and field effect mobility (μ FE ) of 5.4 cm 2 /V · sec. These good performances are related to the high gate capacitance density and small equivalent oxide thickness (EOT) provided by the high-κ LaAlO 3 dielectric. Moreover, the effects of oxygen partial pressure during IGZO deposition process on the device characteristics were investigated. The small SS and low V t allow the devices to be used at operation voltage as low as 1.5 V, which shows the great potential for future high speed and low power applications.With the rapid development of active-matrix flat panel displays (AMFPDs), thin film transistor (TFT) technologies have been widely used for display applications. However, the traditional Si TFTs using amorphous silicon and poly-crystalline silicon as active channel layer face difficulties due to physical drawback properties. 1-3 Recently, the new TFTs with transparent oxide semiconductors have attracted much attention as potential candidates, due to their unique optical and electrical advantages as compared to conventional Si TFTs, such as high mobility, low cost, excellent uniformity, and good transparency to visible light. 4-25 Particularly, indium gallium zinc oxide (IGZO) TFT 7-25 with superior stability and performance is one of the most promising candidates and has been widely studied. Moreover, the IGZO TFTs can be processed with very low thermal budget and used in emerging flexible display applications.With the above merits of IGZO film, the IGZO TFT devices are being considered for a variety of applications, such as low-cost largearea displays, RFIDs and wearable electronics. 7,8 For high-speed display circuits, it requires TFTs to operate at low voltages and high drive currents with low threshold voltage (V t ) and small subthreshold swing (SS), which make low operation voltage TFTs very favorable for efficiency improvement and environment energy conservation. To address these concerns, incorporating high-κ gate dielectric into TFT provides an alternative solution to achieve these goals. [26][27][28] In this paper, we report a low operation voltage IGZO TFT by introducing a high-κ lanthanum aluminum oxide (LaAlO 3 ) 28-30 as gate dielectric. Due to the higher κ-value (∼23) of LaAlO 3 dielectric as compared to that of SiO 2 (∼3.9), the gate capacitance density increases, which lowers the V t and improves the gate leakage current. Besides, the LaAlO 3 dielectric has good reliability of low bias temperature instability among high-κ devices. The LaAlO 3 TFTs showed a small SS of 98 mV/dec, a low V t of 0.29 V, good on-off-state drive current ratio (I on /I off ) of 1.1 × 10 5 , and field effect m...

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A Two-Mask Process for Fabrication of Bottom-Gate IGZO-Based TFTs

Cited by 16 publications

References 8 publications

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process

Low Operation Voltage InGaZnO Thin Film Transistors with LaAlO₃Gate Dielectric Incorporation

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A Two-Mask Process for Fabrication of Bottom-Gate IGZO-Based TFTs

Cited by 16 publications

References 8 publications

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

Teflon/SiO2 Bilayer Passivation for Improving the Electrical Reliability of Oxide TFTs Fabricated Using a New Two-Photomask Self-Alignment Process

Low Operation Voltage InGaZnO Thin Film Transistors with LaAlO3Gate Dielectric Incorporation

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Product

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Low Operation Voltage InGaZnO Thin Film Transistors with LaAlO₃Gate Dielectric Incorporation