A Two‐Step Dry Etching Model for Non‐Uniform Etching Profile in Gate‐All‐Around Field‐Effect Transistor Manufacturing

Abstract

The Gate‐All‐Around Field‐Effect Transistor (GAAFET) is proposed as a successor to Fin Field‐Effect Transistor (FinFET) technology to increase channel length and improve the device performance. The GAAFET features a complex multilayer structure, which complicates the manufacturing process. One of the most critical steps in GAAFET fabrication is the selective lateral etching of the SiGe layers, essential for forming the inner‐spacer. Industry commonly encounters a non‐uniform etching profile during this step. In this paper, a continuous two‐step dry etching model is proposed to investigate the mechanism behind the formation of the non‐uniform profiles. The model consists of four modules: anisotropic etching simulation, Ge atom diffusion simulation, Si/SiGe etch selectivity calculation and SiGe selective etching simulation. By calibrating and verifying this model with experimental data, the edge rounding and gradient etching rates along the sidewall surface are successfully simulated. Based on further examination of the influence of chamber pressure on the profile using this model, the inner‐spacer shape is improved experimentally by appropriately reducing the chamber pressure. This work aims to provide valuable insights for etching process recipes in advanced GAAFETs manufacturing.