A unified addition structure for moduli set &amp;#x007B;2&lt;sup&gt;n&lt;/sup&gt;&amp;#x2212;1, 2&lt;sup&gt;n&lt;/sup&gt;, 2&lt;sup&gt;n&lt;/sup&gt;+1&amp;#x007D; based on a novel RNS representation

Timarchi, Somayeh; Fazlali, Mahmood; Cotofana, Sorin

doi:10.1109/iccd.2010.5647761

Cited by 2 publications

(1 citation statement)

References 22 publications

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“…Here, one solution is using hybrid architectures. For example, instead of designing separate adders for moduli 2 n -1 and 2 n +1, a common adder with a dual output can be designed [14]- [15]. Similarly this approach can be used to combine other parts of the system.…”

Section: A the Holistic Approach To The Design Of Rnsmentioning

confidence: 99%

Research challenges in next-generation residue number system architectures

Molahosseini

Sorouri

Zarandi

2012

2012 7th International Conference on Computer Science &Amp; Education (ICCSE)

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The carry-free nature of residue number system (RNS) has introduced it as an efficient unconventional number system which has attracted lots of researchers for many decades. Distinct aspects of RNS systems such as its application, architectures and implementations were considered. Although, all these researches were done, still lots of leakages exist that need to be fully investigated. Furthermore, new technologies such as nanoelectronics cause extra challenges. In order to facilitate professors, students and all RNS researchers works, we are going to study these emerging challenges in this paper.

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Section: A the Holistic Approach To The Design Of Rnsmentioning

confidence: 99%

Research challenges in next-generation residue number system architectures

Molahosseini

Sorouri

Zarandi

2012

2012 7th International Conference on Computer Science &Amp; Education (ICCSE)

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Modulo 2ⁿ + 1 squarer design for efficient hardware implementation

Modugu

Kim

et al. 2014

2014 International SoC Design Conference (ISOCC)

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In this work, an efficient hardware architecture of modulo 2 n + 1 squarer is proposed and validated. The proposed modulo 2 n + 1 squarer use novel compressor designs and sparse tree adders as primitive building blocks for fast low-power operations in three major functional modules including partial products generation module, partial products reduction module and final stage addition module. The resulting modulo 2 n + 1 squarer has been implemented in standard CMOS (Complementary Metal-Oxide Semiconductor) cell technology and compared both qualitatively and quantitatively with the existing hardware implementations. The unit gate model analysis and the experimental results show that the proposed implementation is faster and consume less power than existing hardware implementations.

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A unified addition structure for moduli set {2<sup>n</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation

Cited by 2 publications

References 22 publications

Research challenges in next-generation residue number system architectures

Research challenges in next-generation residue number system architectures

Modulo 2ⁿ + 1 squarer design for efficient hardware implementation

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A unified addition structure for moduli set &#x007B;2<sup>n</sup>&#x2212;1, 2<sup>n</sup>, 2<sup>n</sup>+1&#x007D; based on a novel RNS representation

Cited by 2 publications

References 22 publications

Research challenges in next-generation residue number system architectures

Research challenges in next-generation residue number system architectures

Modulo 2n + 1 squarer design for efficient hardware implementation

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A unified addition structure for moduli set {2<sup>n</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>+1} based on a novel RNS representation

Modulo 2ⁿ + 1 squarer design for efficient hardware implementation