A unified evaluation framework for coarse grained reconfigurable array architectures

Abstract

The efficiency of a coarse grained reconfigurable array architecture in terms of performance and hardware cost is hard to be determined. The large number of parameters that define an architecture instance and the mapping complexity makes the evaluation extremely difficult to accomplish without tool assistance. This paper investigates the four factors that are directly related with the efficiency of these architectures namely; the area, the clock frequency, the scheduling efficiency and performance. A unified exploration framework has been build for estimating the values of the 4 aforementioned factors for different architecture alternatives. The exploration framework consists of two parts: a) an existing retargetable compiler from which the mapping efficiency is estimated and b) from the parametric realization of the coarse grained reconfigurable array in hardware description language (VHDL). The latter is used for the estimation of the area and clock frequency of each architecture instance with the realization of the system in the 0.13μm process of ASIC technology. Also, the experiments refer to different architecture instances in terms of the processing elements' interconnection network, the register files' size, their number of input output ports, and finally the available bandwidth. Totally 72 architecture scenarios have been studied revealing how each characteristic influences performance and area for efficiently make design decisions.

High-level modelling and exploration of coarse-grained re-configurable architectures

“…The recently proposed ADRES [9] architecture from IMEC, for example, allows to change the parameters like -number and size of register file associated with each basic functional unit, operation set supported by the functional units and interconnect topology -of its re-configurable array. Similar architectural parameters are also found in [10] and [11]. The limitation of such a parameterized approach is that, the introduction of a new design parameter might lead to serious modification in the associated tool-chain.…”

“…For the parameterizable CGRA design flows the RTL generation is often used for simulation [17] [2] but, not for the final implementation. In keeping tune with the parameterized modelling approach, a parameterizable CGRA template using VHDL is described in [10].…”

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

“…Most recently, an unified evaluation framework for coarse-grained reconfigurable architectures, together with a RISC-based processor, has been suggested in Dimitroulakos et al [2007]. The strength of this approach lies in the fact that, the overall system's resulting clock frequency, energy, and area are studied more accurately than other research efforts in this area.…”

Μεθοδολογίες Μεταγλώττισης Σε Επαναπροσδιοριζόμενα Συστήματα Αρχιτεκτονικών Πίνακα.

“…Οι εργασίες [20] και [38] προσεγγίζουν τη διερεύνηση της χαρτογράφησης εφαρµογών σε CGRA από τη µεριά του µεταγλωττιστή πάνω σε ένα πλαίσιο διαφορετικών αρχιτεκτονικών εναλλακτικών και λαµβάνοντας υπόψη την παραλληλία εκτέλεσης των εντολών σε κάθε κύκλο ρολογιού. Μόνο τρεις προσεγγίσεις, οι [41], [43] και [44] • ∆ροµολόγηση δεδοµένων από τους διαύλους δεδοµένων του δικτύου προς τη λειτουργική µονάδα.…”