A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

Abstract

A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness ( LER / LWR ) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design ( TCAD ) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.