2011 Electronic System Level Synthesis Conference (ESLsyn) 2011
DOI: 10.1109/eslsyn.2011.5952296
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A unifying interface abstraction for accelerated computing in sensor nodes

Abstract: Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a lowpower FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/software codesign for sensor node application development. We present the integration of nesC, a sensornet programming… Show more

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Cited by 5 publications
(4 citation statements)
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“…However, [9] has several limitations. First, [9] focuses on the simulation for the processor (MCU) with coprocessor (FPGA). However, our design flow for multiprocessor nodes' applications between simulation and actual hardware development is different.…”
Section: Related Workmentioning
confidence: 99%
See 3 more Smart Citations
“…However, [9] has several limitations. First, [9] focuses on the simulation for the processor (MCU) with coprocessor (FPGA). However, our design flow for multiprocessor nodes' applications between simulation and actual hardware development is different.…”
Section: Related Workmentioning
confidence: 99%
“…In [9], a reusable hardware/software interface between a processor (MCU) and a coprocessor (FPGA) is demonstrated. However, [9] has several limitations.…”
Section: Related Workmentioning
confidence: 99%
See 2 more Smart Citations