A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs

Zhao, Shuze; Ahmed, Ibrahim; Lamoureux, Carl; Lotfi, A.; Betz, Vaughn; Trescases, Olivier

doi:10.1109/apec.2016.7468125

Cited by 19 publications

(10 citation statements)

References 19 publications

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“…Chow et al [21] propose a dynamic voltage scaling scheme that exploits a ring-oscillator based logic delay measurement circuit to mimic the timing behavior of application critical path and adjust the voltage accordingly. However, the inaccuracy of path monitor circuitries in FPGAs and even ASICs has been well elaborated [24], [25], [26], [27]. Levine et al employ timing error detectors inserted as capture registers with a phase-shifted clock at the end of critical paths to find out the timing slack of FPGA-mapped designs through a gradual reduction of voltage [24].…”

Section: Related Workmentioning

confidence: 99%

“…Their approach adds extra area and power overhead, cannot be implemented in paths heading to hard blocks such as memories, and assumes the corresponding paths will be exercised at runtime. Zhao et al propose an elaborated twostep approach by extracting the critical paths of the design using the static timing analysis tool and sequentially mapping into the FPGA [25]. Thence, they vary the FPGA core voltage to obtain the voltage-delay (Vcore − D) relation of the paths for online adjustment during the operation time.…”

Section: Related Workmentioning

confidence: 99%

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Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Salamat

Khaleghi

Imani

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The continuous growth of big data applications with high computational and scalability demands has resulted in increasing popularity of cloud computing. Optimizing the performance and power consumption of cloud resources is therefore crucial to relieve the costs of data centers. In recent years, multi-FPGA platforms have gained traction in data centers as lowcost yet high-performance solutions particularly as acceleration engines, thanks to the high degree of parallelism they provide. Nonetheless, the size of data centers workloads varies during service time, leading to significant underutilization of computing resources while consuming a large amount of power, which turns out as a key factor of data center inefficiency, regardless of the underlying hardware structure. In this paper, we propose an efficient framework to throttle the power consumption of multi-FPGA platforms by dynamically scaling the voltage and hereby frequency during runtime according to prediction of, and adjustment to the workload level, while maintaining the desired Quality of Service (QoS). This is in contrast to, and more efficient than, conventional approaches that merely scale (i.e., power-gate) the computing nodes or frequency. The proposed framework carefully exploits a pre-characterized library of delay-voltage, and power-voltage information of FPGA resources, which we show is indispensable to obtain the efficient operating point due to the different sensitivity of resources w.r.t. voltage scaling, particularly considering multiple power rails residing in these devices. Our evaluations by implementing state-of-the-art deep neural network accelerators revealed that, providing an average power reduction of 4.0×, the proposed framework surpasses the previous works by 33.6% (up to 83%).

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Salamat

Khaleghi

Imani

et al. 2019

2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

show abstract

“…Considering recent works proposing off-line evaluation of critical paths replicas [7], the publications present performance improvement of 50 percent for an FIR filter implemented on a 65 nm Cyclone IV FPGA. Such gain is also within the range of our own framework.…”

Section: Comparison To Similar Methodsmentioning

confidence: 99%

“…In practice, this could mislead the selection of the actual critical paths. The authors in [7] propose an approach to isolate and measure the actual timing slacks of critical paths replicas under various voltage/temperature conditions. Accordingly, they build a calibration table such that, when the target design is mapped on the FPGA, its operation frequency can be adjusted based on the pre-stored values of the calibration table.…”

Section: Related Workmentioning

confidence: 99%

“…Hence, for nominal operation, they ensure functional integrity even for the worst-case scenario of their entire production line. However, this pessimistic approach prevents the majority of the chips from utilizing their full capability and leads to a significant performance loss [6], [7], [8], [9], e.g., 80 percent of potential increase in operation frequency.…”

Section: Introductionmentioning

confidence: 99%

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In-the-Field Mitigation of Process Variability for Improved FPGA Performance

Maragos

Lentaris²,

Soudris³

2019

IEEE Trans. Comput.

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The mitigation of process variability becomes paramount as chip fabrication advances deeper into the sub-micron regime. Conservative guard-bands result in considerable performance loss, while most low-level solutions impede dynamic customization at application level. This paper exploits the existing process variability of commercial off-the-shelf FPGAs to improve the operating frequency of a design, in-the-field, at anytime during the lifetime of a chip. We begin by measuring variability in prevalent FPGAs and assessing its impact on the performance of common DSP benchmarks. For the former, we develop a custom sensing network of Ring-Oscillators to generate detailed 2D maps per chip. For the latter, we perform intensive testing and statistical analysis to establish the relation between variability maps and benchmark frequencies. Accordingly, we propose a framework to automatically characterize the user's devices, place the design on the most efficient region, and scale its frequency based on user requirements and functional verification. Experimental results on 20 FPGAs of 28 nm Xilinx technology show up to 13 percent intra-die and 30 percent inter-die variability; with limited cost, our framework provides 10À14.7 percent average gain by exploiting such variability, or up to 56À138 percent by also customizing the guard-band.

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Analyzing Aging Effects on SRAM PUFs: Implications for Security and Reliability

Bhatta,

Singh,

Ghimire

et al. 2024

J Hardw Syst Secur

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The aging effects on Static Random-Access Memory Physical Unclonable Functions (SRAM PUFs) pose significant security and reliability challenges for current hardware systems. SRAM PUFs utilize process variations in integrated circuits for secure key generation and device authentication. However, aging effects such as bias temperature instability (BTI) and hot carrier injection (HCI) may change SRAM cell characteristics and affect PUF responses. This study addresses various aging-induced variation challenges, identifies security vulnerabilities, and provides innovative approaches to risk reduction. Furthermore, this study focuses on concerns about SRAM PUF reliability. In this regard, mitigation approaches like adaptive reconfiguration, error correction codes, and multi-modal PUFs are introduced to enhance the resilience of SRAM PUFs. This study concludes by outlining future research directions and prospects for improving SRAM PUF-based security solutions by several orders of magnitude. This is carried out with various complexities related to semiconductor device aging.

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A universal self-calibrating Dynamic Voltage and Frequency Scaling (DVFS) scheme with thermal compensation for energy savings in FPGAs

Cited by 19 publications

References 19 publications

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

Workload-Aware Opportunistic Energy Efficiency in Multi-FPGA Platforms

In-the-Field Mitigation of Process Variability for Improved FPGA Performance

Analyzing Aging Effects on SRAM PUFs: Implications for Security and Reliability

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