A universal technique for fast and flexible instruction-set architecture simulation

Nohl, Achim; Braun, Gunnar; Schliebusch, Oliver; Leupers, Rainer; Meyr, H.; Hoffmann, Andreas

doi:10.1109/dac.2002.1012588

Cited by 66 publications

(47 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…New techniques have been proposed to reduce the simulation time, which were presented in [6], [7], [8] and [9]. In particular, a technique called inline tracing can be used to generate the trace of addresses with much less overhead than trapping or simulation.…”

Section: Simulation and Estimation Methods: Overviewmentioning

confidence: 99%

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

Kroupis¹,

Soudris

2010

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

A typical instruction memory design exploration process using simulation tools for various cache parameters is a rather time-consuming process, even for low complexity applications. In order to design a power efficient memory hierarchy of an embedded system, a huge number of system simulations are needed for all the different instruction memory hierarchies, because many cache memory parameters should be explored. Exhaustive search of design space using simulation is too slow procedure and needs hundreds of simulations to find the optimal cache configuration. This chapter provides fast and accurate estimates of a multi-level instruction memory hierarchy. Using a detail methodology for estimating the number of instruction cache misses of the instruction cache levels and power models; we estimate within a reasonable time the power consumption among these hierarchies. In order to automate the estimation procedure, a novel software tool named FICA implements the proposed methodology, which automatically estimates the total energy in instruction memory hierarchy and reports the optimal one.

show abstract

Section: Simulation and Estimation Methods: Overviewmentioning

confidence: 99%

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems

Kroupis¹,

Soudris

2010

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

show abstract

“…Nohl et.al [16] describe generating instruction set simulators using the LISA processor description language. LISA is a domain specific language for describing micro processors.…”

Section: Related Workmentioning

confidence: 99%

Using the CASM language for simulator synthesis and model verification

Lezuo

Krall

2013

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

View full text Add to dashboard Cite

We present the CASM language, an abstract state machine (ASM) based modeling language originally designed for verifying compiler backends. We demonstrate the expressiveness by describing an instruction set simulator (ISS) for MIPS in approximately 700 lines of code. Further we present a refinement of the models to cycle-accurately describe two implementations of the classic 5-stage MIPS pipeline. Utilizing symbolic execution allows us to prove semantic equivalence of the pipeline implementations and the instruction set description. Finally we compile the models to C++ and provide a small runtime to create a system simulator achieving a performance of approx. 1 MHz in MiBench and SPECInt2000 benchmarks.

show abstract

“…For example, decoding stage of the pipeline can be performed in compilation time. Then, depending on the result of this stage, the simulation compiler selects the native operations required to simulate the application (Nohl et al, 2002). Compiled simulations based on architectural description languages have been developed in different projects, such as Sim-nML (Hartoog et al, 1997), ISDL (XSSIM) (Hadjiyiannis et al, 1997) y MIMOLA (Leupers et al, 2099).…”

Section: Related Workmentioning

confidence: 99%