A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

Abbas, Waseem; Mehmood, Zubair; Seo, Munkyo

doi:10.3390/electronics9091502

Cited by 7 publications

(3 citation statements)

References 21 publications

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“…VCDL [2] VCDL [3] VCDL [4] VCDL [5] VCDL [6] VCDL [7] VCDL [8] Σ VCDL 6, it can be seen that the pulse width of the MD is expressed longer than one cycle. The wider UP signal is required, whereas the DN signal is not needed.…”

Section: Ref Vcdl [1]mentioning

confidence: 99%

“…The methods using a time-to-digital converter (TDC) [12] or extra replica delay cells [13] consumed high power and required a large area. Several studies have been conducted to solve the false locking problem caused by using this simple PD structure [2][3][4][5][6][7][8][9][10][11][12][13]. The technique in [6] using an external reset pulse makes it possible to escape from the false lock state, but does not actively respond to situations such as sudden changes in the reference signal.…”

Section: Introductionmentioning

confidence: 99%

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A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

Cho

2022

Electronics

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A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

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Section: Ref Vcdl [1]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

Cho

2022

Electronics

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“…As a result the output should be oscillating in nature with satisfying the gain of a close loop system (larger than 1); the initial standard is met. Toward the second standard (achieve a phase shift of 180°), minimum 3-holdup cell are requisite [5,6]. The propagation delay is shown in the Fig.…”

Section: Introductionmentioning

confidence: 99%

Ring Oscillator for 60 Meter Bandwidth

Arya¹,

Singh²

2023

Computer Systems Science and Engineering

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The 60-meter band range is tremendously useful in telecommunication, military and governmental applications. The I. T. U. (International Telecommunication Union) required isolationism to former radio frequency services because the various frequency bands are extremely overloaded. The allocation of new frequency bands are a lengthy procedure as well as time taking. As a result, the researchers use bidirectional, amateur radio frequency communication for 60meter band, usually the frequency slot of 5250-5450 KHz, although the entire band is not essentially obtainable for all countries. For transmission and reception of these frequencies, a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals. For this function different type of oscillators are used. In this paper, a three-stage ring oscillator is designed with 1 V supply. Ring oscillators (RO) is the base to explore like to identifying, specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters. This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator, Heartly oscillator, Colpitt and tuned oscillators. The present approach of circuit designing, the scaling of CMOS (Complementary Metal Oxide Semiconductor) transistor will moderate, the procedure variability. In the forthcoming article, a ring oscillator with fixed capacitor (1 pF) and with variable capacitors (1 to 100 pF) is analysed. The frequency analysis with different capacitor is performed. The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency. The overall Power dissipation of the circuit is 1.852 μW at 1 V supply. The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

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Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nano Dimensional MOS Transistors at 16 nm, 22 nm, 32 nm

Valasa¹,

Tayal²

2022

Lecture Notes in Electrical Engineering

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A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

Cited by 7 publications

References 21 publications

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

Ring Oscillator for 60 Meter Bandwidth

Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nano Dimensional MOS Transistors at 16 nm, 22 nm, 32 nm

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