A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

Kaur, Baljit; Sharma, Arvind Kumar; Alam, Naushad; Manhas, S. K.; Bulusu, Anand

doi:10.1016/j.mejo.2016.03.010

Cited by 5 publications

(3 citation statements)

References 23 publications

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“…While this result is interesting, it seems quite high especially that tests on full circuit haven't been done [15]. Other works proposed other methodologies of standard cells characterization but they still require a high amount of running time [16][17][18].…”

Section: Introductionmentioning

confidence: 95%

New voltage and temperature scalable gate delay model applied to a 14nm technology

Charafeddine

Ouardi

2020

IJEECS

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<p>The following work shows an innovative approach to model the timing of standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work, characterization of cells of a standard cell library is done in an hour whereas it is done in 650 hours with the classical method. Also, a method for validating and verification of the precision of the modelled data is presented by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>

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Section: Introductionmentioning

confidence: 95%

New voltage and temperature scalable gate delay model applied to a 14nm technology

Charafeddine

Ouardi

2020

IJEECS

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“…These sources influence the device electrical figures of merit such as threshold voltage (Vth), off-state current and Subthreshold Slope (SS) which in turn they will make a significant impact on the circuit behavior. In particular, the impact of process and random variability on the propagation delay time is widely studied in the literature [12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

“…The propagation delay variation due to RDF at different technology nodes is comprehensively studied in [13]. A variation-aware timing model for a twoinput NAND gate is proposed in [14] for 65-nm technology node. Authors in [15] have investigated statistical estimation of delay in nano-CMOS circuits using Burr distribution.…”

Section: Introductionmentioning

confidence: 99%

Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters

2021

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In this paper, we model statistical correlation between overshooting effect and propagation delay time in nano-CMOS technology considering the influence of intrinsic parameter fluctuations caused by discreteness of charge and granularity of matter. The impact of input slew rate, output capacitive load, and supply voltage on this statistical correlation is comprehensively studied. Moreover, we propose two alternative approaches which are capable of reproducing the statistical correlation as well as mean and standard deviation of both propagation delay time and overshoot voltage. We evaluate the accuracy of these alternative approaches against accurate Monte-Carlo simulations. It is shown that the statistical correlations are almost preserved using these alternative approaches.

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Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells

Reddy

Jayasree

2019

Sustainable Computing: Informatics and Systems

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A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization

Cited by 5 publications

References 23 publications

New voltage and temperature scalable gate delay model applied to a 14nm technology

New voltage and temperature scalable gate delay model applied to a 14nm technology

Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters

Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells

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