2013
DOI: 10.1007/s11265-013-0744-4
|View full text |Cite
|
Sign up to set email alerts
|

A Very High Throughput Deblocking Filter for H.264/AVC

Abstract: International audienceThis paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less f… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
5

Citation Types

0
5
0

Year Published

2015
2015
2023
2023

Publication Types

Select...
7
3

Relationship

0
10

Authors

Journals

citations
Cited by 10 publications
(5 citation statements)
references
References 11 publications
0
5
0
Order By: Relevance
“…Using a Low-Level Synthesis design, the Register Transfer Level (RTL) description may be adjusted to generate an excellent and efficient netlist. Developing an RTL description is arduous and time-consuming, particularly for complicated applications [52][53][54]. In fact, each low-level circuit's operations must be specified.…”
Section: Introductionmentioning
confidence: 99%
“…Using a Low-Level Synthesis design, the Register Transfer Level (RTL) description may be adjusted to generate an excellent and efficient netlist. Developing an RTL description is arduous and time-consuming, particularly for complicated applications [52][53][54]. In fact, each low-level circuit's operations must be specified.…”
Section: Introductionmentioning
confidence: 99%
“…The density of Field Programmable Gate Arrays (FPGAs) has increased over time, enabling hardware implementation of complex applications across various fields, such as IoT systems [20], video processing [21,22], and neural networks [23]. To reduce the design complexity of FPGAs, High-Level Synthesis (HLS) flow can be employed instead of Low-Level Synthesis (LLS) flow, allowing for efficient exploration of an algorithm's design space and increased designer productivity [24,25].…”
Section: Introductionmentioning
confidence: 99%
“…With LLS design, the Register Transfer Level (RTL) description can be modified to produce an excellent, efficient netlist. However, creating such an RTL description takes a lot of work and time, especially for complicated applications [ 50 , 51 , 52 ]. This is because each low-level circuit’s activities must be described.…”
Section: Introductionmentioning
confidence: 99%