A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 $\mu$ m SiGe BiCMOS

Wagner, Eric; Shanaa, Osama; Rebeiz, Gabriel M.

doi:10.1109/tmtt.2019.2957372

Cited by 32 publications

(15 citation statements)

References 31 publications

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“…Figure 3 presents the simulated phase noise comparisons of VCO1 (when V bit1 and V bit2 are set to "11") between the kept-constant current case (1.0 mA) and the switched current case (2.0 mA). As shown in Figure 3, when the reference current is switched from 1.0 mA to 2.0 mA, the phase noise can be reduced by 6.4 dB, which agrees well with the theoretical value of 6.0 dB which is calculated according to (1). And the simulated FOM can be reduced by 3.4 dB according to (5).…”

Section: Four-core Vco Arraysupporting

confidence: 85%

“…One challenge in these systems is the strict phase noise and bandwidth requirements of the phase-locked loop (PLL), which is typically in the range of 8 ~20 GHz. 1,2 Also, this frequency range is relevant for Xand Ku-bands radar systems. Silicon-Germanium heterojunction bipolar transistors (SiGe HBTs) are of great interest for these applications, because this device technology can combine high-frequency and low-noise operation and allow a high degree of integration.…”

Section: Introductionmentioning

confidence: 99%

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X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

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Section: Four-core Vco Arraysupporting

confidence: 85%

Section: Introductionmentioning

confidence: 99%

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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“…The 1st stage of 9 GHz RSPLL achieves a 144 fs integrated jitter with 7.2 mW power consumption and the overall mmwave synthesizer achieves a tunable range of 33.6-36 GHz with a phase noise of −94.9 dBc Hz −1 at 1 MHz offset frequency for 35.84 GHz. In [61], a class-C type transformercoupled VCO is combined with type II charge-pumped-based PLL based on 0.12 µm SiGe technology. This proposal generates an mm-wave signal whose frequencies are 20-24 GHz and 30-36 GHz by multiplying the fundamental frequency of 10-12 GHz.…”

Section: Vco and Pllmentioning

confidence: 99%

“…Aforementioned, the RX system noise mainly consists of the 31 dB SNR, the ADC quantization noise, the ADC clock jitter, and the phase noise of LO. When the modualted format is the 64 QAM, the total RX EVM is estimated as 4% and the part caused by phase noise is approximate 2.5% in the RX [61]. According to the equation (17), the phase jitter is equal to 0.025 rad and the power ratio is −32 dB, while the integration range is from 50 kHz to 800 MHz.…”

Section: Requirement Of Phase Noisementioning

confidence: 99%

Optoelectronic oscillator for 5G wireless networks and beyond

Zou

Yang

et al. 2021

J. Phys. D: Appl. Phys.

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With the development of 5G wireless network and beyond, the wireless carrier frequency will definitely reach millimeter-wave (mm-wave) and even terahertz (THz). As one of the key elements in wireless networks, the local oscillator (LO) needs to operate at mm-wave and THz band with lower phase noise, which becomes a major challenge for commercial LOs. In this article, we investigate the recent developments of the electronic integrated circuit (EIC) oscillator and the optoelectronic oscillator (OEO), and especially investigate the prospect of OEO serving as a qualified LO in the 5G wireless network and beyond. Both the EIC oscillators and OEOs are investigated, including their basic theories of operation, representative techniques and some milestones in applications. Then, we compare the performances between the EIC oscillators and the OEOs in terms of frequency accuracy, phase noise, power consumption and cost. After describing the specific requirements of LO based on the standard of 5G and 6G wireless communication systems, we introduce an injection-locked OEO architecture which can be implemented to distribute and synchronize LOs. The OEO has better phase noise performance at high frequency, which is greatly desired for LO in 5G wireless network and beyond. Besides, the OEO provides an easy and low-loss method to distribute and synchronize mm-wave and THz LOs. Thanks to photonic integrated circuit development, the power consumption and cost

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“…Since the PLL is intended to deliver its output signal to a transceiver on the same chip in the future prototype, and this mm-wave buffer is mainly for testing purposes, its power has not been counted. ISSCC'19 [166] ISSCC'20 [167] TMTT'17 [168] ISSCC'16 [169] TMTT'20 [170] ISSCC'19 [171] This work The standard metrics for PLL performance quality are ℒnorm [160], FoM [145], and FoMJRP [165] described as follows:…”

Section: Measurement Resultsmentioning

confidence: 99%

Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops

Liu¹

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The future 6G network and big-data center will be generating and capturing a wealth of data that was previously unimaginable. The conventional inter-server interconnects rely on optical cables that can reach Tera-scale; however, they are not fully based on integrated circuit (IC) processes and hence cannot be scaled down for both cost and power. Full integration in the complementary metal-oxidesemiconductor (CMOS) technologies has been identified as the ultimate solution to build the low-cost, low-power, highly compact interconnect that meets the stringent requirement of next generation 100/400 GbE communication. Unfortunately, silicon channels suffer from strong electromagnetic crosstalk (and loss) at high speed with limited output power generated by the signal source. To overcome such issues, conventional data interfaces have implemented crosstalk-compensated equalizers and signal source leading to an excessively high 5-20 pJ/bit power efficiency. Furthermore, crosstalk-compensated equalizers have limited speeds up to 13 Gb/s.Recently, the integrated surface plasmonic polaritons (SPPs) components and circuits were proposed and implemented in silicon at the ultra-broadband terahertz (THz) frequency toward high-speed, lowpower, low-crosstalk signaling. The surface plasma (or surface wave) is a special electromagnetic (EM) wave to localize the free electron into the metal/medium interface, achieving extraordinary field confinement and enhancement. Implemented in advanced CMOS technologies, the design will be smaller, lighter, cheaper, and scalable for emerging applications such as low-crosstalk digital signaling, ultrahigh-speed communication, low-power transceiver, remote sensing, and threat detection.As there is a lack of knowledge on how to achieve surface plasmonic generation, transmission, modulation, conversion, and amplification in silicon, this thesis aims to conceptualize, design, implement, and validate several on-chip high-performance metadevices. Several I/O interface architectures are reviewed in Chapter 2, followed by the introduction of SPPs fundamentals, design, and comparison to conventional on-chip transmission lines. The impact of channel crosstalk on bit-error rate (BER) as well as power consumption will be evaluated based on link budget analysis. To evaluate how plasmonic can attenuate the channel crosstalk, the surface wave transmission lines (T-line) are modeled on the T-section network incorporated by the lossy T-line model. This model can also describe the impedance, phase shift, dispersion behavior, and loss of the surface plasmonic T-line from the circuit's perspective. Like other surface plasmonic T-lines implemented on the printed circuit boards (PCBs), impedance or momentum mismatch occurs between the TEM devices and the plasmonic devices. A gradient groove plasmonic converter is designed and experimentally verified in Chapter 3. Since the coplanar waveguide (CPW) is not involved for impedance conversion, the design is compact and therefore suitable for on-chip implementation.A split-...

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A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 $\mu$ m SiGe BiCMOS

Cited by 32 publications

References 31 publications

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Optoelectronic oscillator for 5G wireless networks and beyond

Siliconization of millimeter-wave to terahertz surface-plasmonic transceiver and phase-locked loops

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