A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs

Schumacher, P.; Mattavelli, Marco; Chirila-Rus, A.; Turney, Robert D.

doi:10.1109/icme.2005.1521562

“…In order to implement the full HW/SW co-design, we used a prototyping platform developed by Calgary University and the MPEG/ISG group [26,27]. The platform is based on a standard PC and a single PCMCIA FPGA-based board.…”

Section: Prototyping Platform and Design Methodologymentioning

confidence: 99%

An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM

Smach

¹

,

Mitéran

²

,

Atri

³

et al. 2007

J Real-Time Image Proc

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“…Some research works concentrated on tools that can optimize task partitioning for applications such as Multimedia (e.g. [25,12,95]), DSP and Digital Communication (e.g. [5]).…”

Section: Literature Reviewmentioning

confidence: 99%

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

0

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The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

show abstract

“…Some research works concentrated on tools that can optimize task partitioning for applications such as Multimedia (e.g. [25,12,95]), DSP and Digital Communication (e.g. [5]).…”

Section: Literature Reviewmentioning

confidence: 99%

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

Kirischian¹

2021

Preprint

0

View full text Add to dashboard Cite

The main motivation factors for the proposed research were the increase of cost-efficiency of FPGA based systems and the simplification of the design process. The first factor is optimization of design in multi-parametric constraint space. The second factor is the design of reconfigurable systems based on higher level of abstraction in a form of macro-functions rather than conventional HDL primitives. Main goal of this work was to create a methodology for automated cost-effective design synthesis of FPGA systems by utilizing temporal partitioning concept. Temporal partitioning provides powerful mechanism that allows to design cost-effective multi-parametrically optimized architectures. Another feature of these architectures is the ability for run-time self-restoration from hardware faults. As the result of the proposed research this methodology was created and successfully verified on the first prototype of Multi-mode Adaptive Reconfigurable System (MARS) with embedded Temporal Partitioning Mechanism (TPM). A special CAD software system was developed for automated application programming, automated task segmentation, and further high-level synthesis of segment specific processors (SSPs). Several novel methodologies were proposed, developed, and verified including: a methodology for creation of macro-operators (MOs) and associated set of optimized virtual hardware components (VHCs); an automated task segmentation methodology and synthesis of segment specific processors from the VHCs; methodology for integration of fault tolerance mechanisms with the self-restoration capability. The latter mechanism made possible the mitigation of transient and permanent hardware faults in run-time. The proof-of-concept component of this research consists of implementation of the above methodologies and mechanisms in the special software CAD system and verification on the experimental setup based on the prototype of system with TPM (MARS platform). As the result, all the developed methodologies and architectural solutions were tested and their effectiveness was demonstrated.

show abstract

A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs

Cited by 5 publications

References 4 publications

An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM

An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

The methodology of synthesis of dynamically reconfigurable computing systems with temporal partitioning of homogeneous resources

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