A VLSI algorithm for modular multiplication/division

Kaihara, Marcelo E.; Takagi, Naofumi

doi:10.1109/arith.2003.1207682

Cited by 7 publications

(7 citation statements)

References 9 publications

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“…As the number of multiplications and divisions are proportional to the weight of the exponent, acceleration can be accomplished by representing the exponent as a minimum weight SD2 number. Finally, it is worth noting that these operations can still be computed using the Montgomery representation as described in [5].…”

Section: Discussionmentioning

confidence: 99%

“…In a previous publication [5], we proposed a hardware algorithm for modular multiplication/division that calculates modular division and Montgomery multiplication where the calculation of the modular division is based on the extended Binary GCD algorithm. In this paper, we propose a hardware algorithm for modular multiplication/division which calculates modular division, Montgomery multiplication, and also, ordinary modular multiplication with similar hardware resources to that necessary to calculate modular division only.…”

Section: Introductionmentioning

confidence: 99%

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A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

Kaihara

Takagi

2005

IEICE Transactions on Fundamentals of Electronics, Communicatio

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A hardware algorithm for modular multiplication/division which performs modular division, Montgomery multiplication, and ordinary modular multiplication is proposed. The modular division in our algorithm is based on the extended Euclidean algorithm. We employ our newly proposed computation method that consists of processing the multiplier from the most significant digit first to calculate Montgomery multiplication. Finally, the ordinary modular multiplication is based on shift-and-add multiplication. Each of these three operations is carried out through the iteration of simple operations such as shifts and additions/subtractions. To avoid carry propagation in all additions and subtractions, the radix-2 signed-digit representation is employed. A modular multiplier/divider based on the algorithm has a linear array structure with a bit-slice feature and carries out n-bit modular multiplication/division in O(n) clock cycles, where the length of the clock cycle is constant and independent of n. This multiplier/divider can be implemented using a hardware amount only slightly larger than that of the modular divider.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

Kaihara

Takagi

2005

IEICE Transactions on Fundamentals of Electronics, Communicatio

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“…As shown in Fig. 5, ETB (111) GOI n-MOSFETs are expected to achieve high performance in future advanced nano-sheet channels [6,7,33,34]. In order to realize this device, (111) GOI wafers on Si substrates were fabricated by using the smart-cut technology [35][36][37].…”

Section: Experimental Examination Of Etb Goi Channel P-fetsmentioning

confidence: 99%

(Invited) Extremely-Thin Body Goi Channel Technology in Nano-Sheet FET Era

Takagi¹,

Chen²,

Han³

et al. 2022

ECS Trans.

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Extremely-thin body (ETB) nano-sheet CMOS is expected as a device structure to realize future continuous scaling. Thus, channel materials to maintain high mobility in such an ETB channel are strongly needed. It is revealed through analyses based on a new physical model of thickness fluctuation scattering that ETB GOI channels, particularly (111) GOI channels, are promising for this purpose. High-quality ETB GOI channels are formed by the Ge condensation and smart-cut technology. The operations of Ge p- and n-MOSFETs with the body thickness down to 2 nm are experimentally demonstrated and the body thickness dependencies of the effective mobility are examined. The importance of strain and surface orientation engineering on mobility in an ETB region is addressed.

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“…Trial division of a number by the modulus is one way of performing modular reduction and a piece of hardware especially designed to perform multi precision modular division will perform far better than a general purpose processor. Kaihara and Takagi propose a hardware algorithm capable of performing the modular division operation in O(n) cycles, where n is the bitlength of the operands [2].…”

Section: Rsa Accelerationmentioning

confidence: 99%

Queen's University of Belfast

1935

The Lancet

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A VLSI algorithm for modular multiplication/division

Abstract: We propose an algorithm for modular multiplication + 3 clock cycles and an n-bit modular division in at most 2n+5 clock cycles, where the length of the clock cycle is constant and independent of n.

Cited by 7 publications

References 9 publications

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm

(Invited) Extremely-Thin Body Goi Channel Technology in Nano-Sheet FET Era

Queen's University of Belfast

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