A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

Abstract

In this paper we propose a novel VLSI artwork modification technique based on the concept of a minimum layoutperturbation. Layouts are designed so that minimum design rules must be satisfied. Often layout processes such as custom layout methodologies and design rule migration activities introduce design rule violations in layouts. A minimum layout perturbation defines a minimum cost change to a layout, such that the resulting layout satisfies all design rules. We formulate the minimum perturbation cost with the objective of preserving as much as possible the geometric and topological features of the original layout. The proposed minimum perturbation problem formulation is transformed into a linear programming problem with special structure. We exploit the structure of the problem to propose efficient algorithms that solve the problem. We also propose and implement a practical graph-based simplex algorithm, which we compare to a commercially available linear programming package, resulting in more than 40X performance improvements in some cases. Finally, the proposed methods have been implemented and used in real life problems, for example in the technology migration of data path macros and a 30O-cell gate array library.

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…Mixed integer linear programming formulations and dynamic programming algorithms have been proposed to enable DSA-friendly cut mask designs [35], [36], [48], [49]. Given a set of design rules, line-end extension problems aforementioned are similar to the layout migration issue [20], where the objective is to minimize the amount of dummy patterns and the design rules are formulated as linear constraints. The (mixed integer) linear programming based line-end extensions can help to obtain lithography-friendly layout, which greatly reduces the amount of engineering-changingefforts for routing closure.…”

Topology-driven cell layout migration with collinear constraints

“…Only the work by Lakos [6] addressed wire extraction. This study proposes a fast and efficient polygon-to-wire extraction algorithm based on iterative polygon shrinking.…”

“…The bulky burden lowers the availability of layout migration. Heng et al proposed a minimum perturbation (MP) objective function to preserve original design intention by minimizing the position changes of all edges [6]. To improve the MP objective function, Fang et al considered that the effect of geometric changed by accumulating the effect of position changing in subsequently processed objects [7].…”

“…Currently available layout migration algorithms were classified into constraint graph based [1,2,3] and integer linear programming based [4,5,6,7] algorithms. Constraint graph based algorithms usually scans all components via a virtual scan line of the design and then constructs a constraint graph.…”

A graph based simplex method for the integer minimum perturbation problem with sum and difference constraints

“…. , an ≥ 0 and all variables and constants are integers.The minimum perturbation problem [6] arose from layout migration. The sum and difference constraints arose from the hierarchical nature of the layout.…”