A VLSI - ASIC implementation of Fast Hartley transform for OFDM receivers

Kannan, P. Magesh; Govindarajan, Karthik; Pulli, A.

doi:10.1109/icsccn.2011.6024623

Cited by 1 publication

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…IV. ASIC IMPLEMENTATION Area, power dissipation and speed are the most important factors when it comes to implementation of high end systems in VLSI domain [13]. The integrated design of 16-channel Tx and Rx beamformer has been simulated using Synopsys VCS (Verilog Compiler Simulator), synthesized using DC (Design Compiler) and implemented the complete physical design using ICC (Integrated Circuit Compiler).…”

Section: Receive Beamforming Architecturementioning

confidence: 99%

Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging

Dusa

Kalalii

Rajalakshmi

et al. 2015

2015 28th International Conference on VLSI Design

View full text Add to dashboard Cite

Abstract-In commercial ultrasound systems, the multielement transducer array is connected to analog front end electronics using long-wire high voltage coaxial cables. This paper presents the circuit design of 16-channel Transmit (Tx) and Receive (Rx) beamforming ASIC (Application Specific Integrated Circuit) that can be integrated in ultrasound probe head which reduces the number of coaxial cables. The proposed modular design for programmable 16-channel transmit beamformer operates at medical frequencies in pulse-echo mode and provides user control of transmit parameters such as transmit pulse length, pulse pattern, transmit frequency, and mode of excitation. The receive beamformer implements delay and coherent sum of the digitized echoes from 16 adjacent transducer elements to form scanlines required for image reconstruction. The proposed architecture of the Rx beamformer design provides great flexibility for beamforming, such as receive focusing with predetermined delay profile. Each transmit channel can be programmable to give a maximum delay of 163.85 µs with 1.25 ns delay resolution. The proposed design implements dynamic receive focusing with minimum time delay resolution of 3.125 ns for 40 MHz input data rate. The proposed ASIC of integrated Tx and Rx beamformer is implemented in UMC 130 nm technology using Synopsys ICC and Design Compiler. The implementation reports show that the area is 5.29 mm 2 , power dissipation is 38 mW.

show abstract

Section: Receive Beamforming Architecturementioning

confidence: 99%