A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

Shimazaki, Kosuke; Yoshizawa, Shingo; Hatakawa, Yasuyuki; Matsumoto, Tomoko; Konishi, Satoshi; Miyanaga, Yoshikazu

doi:10.1587/transfun.e96.a.2114

Cited by 2 publications

(3 citation statements)

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“…As it is shown, the throughput performance of our MPSoC design approaches the performance achieved by ASIC [7], and outperforms the combined ASIP+ASIC architecture [8]. However, the area and the power efficiencies of our design are inferior to the other two designs.…”

Section: Comparison With State-of-art Asicsmentioning

confidence: 62%

“…The area consumption of the Ref. [8] consists both the ASIP core and the ASIC for THP, and the cycle counts that include the THP processing are calculated by adding up the cycles used to perform QRD and the scaled cycles to process 12 vectors by THP.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…To the best of our knowledge, only a few ASIC implementations [7] that incorporate sorting operations have been reported. Most of the architectures [8][9][10] that calculate QRD didn't consider it.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Octopus: A Flexible, Efficient MPSoC Prototype for Non-linear Interference Cancellation

Ling¹,

Tang²,

Liu³

et al. 2016

Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications

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Abstract. Many non-linear (NL) interference cancellation (IC) algorithms characterize vector based operations instead of matrix operations, and their performance can be further improved by a proper sorted preprocessing of the channel information, e.g., successive interference cancellation (SIC) and Tomlinson-Harashima precoding (THP) for multi-user multiple-input and multiple-output (MIMO) communication systems. However, on the one hand, application-specific architectures are efficient but not flexible in performing NL IC algorithms; on the other hand, existing single-core based flexible architectures aimed for intensive matrix operations are not efficient when mapping these algorithms. Alternatively, the multiprocessor system-on-chip (MPSoC) architecture can provide better diversity to implement demanding NL algorithms. This paper proposes an efficient and programmable MPSoC prototype to bridge the efficiency and flexibility gap, especially for versatile Gram-Schmidt process (GSP) aided NL IC algorithms. This prototype incorporates several slave processors and one master processor based on the division of computing and control of the mapped algorithms. The slave processor integrates a coarse-grained programmable element (CGPE) with special support for atomic vector operations, while the maser processor is responsible for task schedule and data transportation among slave processors and memories. For demonstration, a tightly coupled sorted QR decomposition (SQRD) aided THP is mapped to the proposed MPSoC, where a speculative dynamic runtime schedule (SDRS) strategy is applied to reduce the computational delay. The synthesis results are presented to show the efficiency and feasibility of our MPSoC prototype.

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Section: Comparison With State-of-art Asicsmentioning

confidence: 62%

Section: Implementation Resultsmentioning

confidence: 99%