A VLSI High-Performance Priority Encoder Using Standard CMOS Library

Abdel-Hafeez, Saleh; Harb, Shadi M.

doi:10.1109/tcsii.2006.876412

Cited by 22 publications

(14 citation statements)

References 8 publications

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“…In comparison with [5], which was simulated in 150-nm CMOS technology, current designs gradually become better when PE sizes vary from 32-bit to 256-bit. As seen in Fig.…”

Section: Performance Analysismentioning

confidence: 99%

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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Abstract-In our prior study of an L-bit priority encoder (PE), a so-called one-directional-array to two-directional-array conversion method is deployed to turn an L-bit input data into an M × N-bit matrix. Following this, an N-bit PE and an M-bit PE are employed to obtain a row index and column index. From those, the highest priority bit of L-bit input data is achieved. This brief extends our previous work to construct a scalable architecture of high-performance large-sized PEs. An optimum pair of (M, N) and look-ahead signal are proposed to improve the overall PE performance significantly. The evaluation is achieved by implementing a variety of PEs whose L varies from 4-bit to 4096-bit in 180-nm CMOS technology. According to post-placeand-route simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times, 1.5 times, and 1.4 times, as high as state-of-the-art ones.

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“…In comparison with [5], which was simulated in 150-nm CMOS technology, current designs gradually become better when PE sizes vary from 32-bit to 256-bit. As seen in Fig.…”

Section: Performance Analysismentioning

confidence: 99%

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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“…In FP arbiters [12] , each master is assigned a fixed value as its priority. When several masters request simultaneously, the master with the highest priority will be granted.…”

Section: Fp Arbitersmentioning

confidence: 99%

An Asynchronous Adaptive Priority Round‐Robin Arbiter Based on Four‐Phase Dual‐rail Protocol

Yang¹,

Wu²,

Zhang³

et al. 2015

Chin. j. electron.

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“…In general, most previous studies of PE attempted to either improve the conventional architecture or minimize the number of used transistors, thereby reducing latency, resources, and power [6,7,8]. These improvements were successfully applied in applications such as incrementers/decrementers [9], comparators [10], and ternary content-addressable memory [11].…”

Section: Introductionmentioning

confidence: 99%

An FPGA approach for high-performance multi-match priority encoder

Nguyen

Pham

2016

IEICE Electron. Express

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In this paper, a scalable high-performance multi-match priority encoder (MPE) for information retrieval is presented. This approach deploys a new design architecture to construct the large-sized MPEs by using an 8-bit priority encoder as a basement. The experiments in an 8-bit MPE, 64-bit MPE, and 2,048-bit MPE prove that the achieved throughputs are 1.5 times, 1.7 times, and 1.4 times as high as those of previous works. Furthermore, a 4,096-bit MPE is fully operational in an information retrieval system and is capable of returning one match per clock cycle. At the operating frequency of 75 MHz, the processing time in worst and best case are 54.6 µs and 0.03 µs, respectively.

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A VLSI High-Performance Priority Encoder Using Standard CMOS Library

Cited by 22 publications

References 8 publications

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

An Asynchronous Adaptive Priority Round‐Robin Arbiter Based on Four‐Phase Dual‐rail Protocol

An FPGA approach for high-performance multi-match priority encoder

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