A voltage scaling model for performance evaluation in digital CMOS circuits

Exploration of Device Design Space to Meet Circuit Speed Targeting 22nm and Beyond

“…Thus, the delay is less sensitive to I on . For the same balanced NMOS and PMOS, I eff of NAND and NOR circuits [4] are much smaller than that of the inverter. The delay is more sensitive to DIBL, I off and V dd , since the percentage change of I eff due to a certain DIBL, I off and V dd is larger for NAND and NOR which have a smaller nominal I eff than inverter.…”

“…In NAND and NOR circuits, the stacked devices operate in the linear region most of the time [4]. For a balanced design with the same equivalent I on as inverters, NAND and NOR gates have larger gate capacitances, thus the switching trajectory of the parallel devices in NAND and NOR chains are further from the saturation point than the inverter chains since the devices are turned on more slowly.…”

“…Instead, the whole trajectory of the device operating points matters. [2][3][4][5] studied the impact of different regions of device IV characteristics on the circuit delay performance and developed different effective current metrics for a better estimation of the circuit delay. On the other hand, at the device level, MOSFETs are benchmarked by characteristics such as on-state drain current (I on ), off-state drain current (I off ), DIBL, current booster factor (k vs ) and so on.…”