A wide input range, external capacitor-less LDO with fast transient response

Abstract

A high voltage, external capacitor-less low-dropout regulator (HVLDO) with transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage laterallydiffused MOS (LDMOS) transistors and a transient enhancement loop is proposed to properly inject/sink current to/from the gate and output nodes of the power transistors to achieve fast transient response and high stability. Fabricated in 0.5 μm SOI BCD process, the HVLDO occupies an active area of 0.29 mm 2 . Operating with an input voltage ranging from 5.2 to 20 V, it supplies an output voltage of 5 V and a maximum load of 100 mA. For all load conditions, this design has the power supply rejection of -49 dB@ 100 kHz, the phase margin over 68.4 deg and achieves a temperature coefficient of 13.15 ppm/°C. Measurement results show that this design has a line regulation of 0.88 mV/V and a load regulation of 0.22 mV/mA. The proposed HVLDO features fast line transient response of 60/20 mV@ 9.8 V/µs, fast load transient response of 30/70 mV@100 mA/µs, and recovery time of 2 µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19 fs.

Design of high-reliability LDO regulator incorporated with SCR based ESD protection circuit using transient switch structure

“…The proposed transient switch structure forms a path that can supply and discharge additional current in accordance with changes in load current. As a result, it can be confirmed that the proposed LDO regulator can effectively control output voltage according to load current changes due to the formation of an additional current path[13,14,15,16,17,18,19,20].…”

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

“…Figure 1 shows a simplified block diagram of the proposed OCL-LDO. The OCL-LDO includes a fast feedback loop [17][18][19], a reference circuit, an error amplifier for comparing the difference between the feedback and reference voltage, and a DFC provides frequency compensation [20][21][22]. A detailed circuit of the error amplifier and DFC is shown in Figure 2.…”

High-reliability LDO regulator with built-in SCR-based ESD protection circuit designed for effective peak voltage reduction

“…As a result, if the LDO regulator generates a large peak voltage in response to a change in load current, a situation arises in which it cannot provide an appropriate voltage to the system to which it is connected. Therefore, the LDO regulator must be configured to operate stably regardless of the change in load current [1,2,3,4,5,6,7,8]. As shown in Figure 1, it is not common to protect an IC circuit with a built-in ESD protection circuit.…”