A wide-range delay-locked loop with a fixed latency of one clock cycle

Abstract

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1 (max) to 1 (3 min), where min and max are the minimum and maximum delay of a delay cell, respectively, and is the number of delay cells used in the delay line. Fabricated in a 0.35-m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 m 515 m and consumes a maximum power of 132 mW at 130 MHz.

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

“…Therefore, the design and optimization of the PD are essential for achieving high-performance DLLs in various applications. The conventional reset-path based PD is widely used because of its dead-zone free ability, as shown in Figure 2 [1][2][3]. The phase detector consists of two D flip-flops and an AND gate on the reset path.…”

Asynchronous delay doubler and binary low‐pass filter for a time‐delay chaotic circuit

“…Some designs require the run-time tunability of the delay time, in order to compensate the delay deviation with a negative feedback. The most practical example of such systems is the delay-locked loop (DLL), which is a servomechanism that controls a delay line in order to match the phases of a reference signal and the signal generated by the delay line [1]. Voltage-controlled delay cell is one of the basic blocks for DLLs.…”