A wide range programmable duty cycle corrector

Jaiswal, AK; Fang, Yuan; Nawaz, Kashif

doi:10.1109/socc.2013.6749686

Cited by 7 publications

(2 citation statements)

References 12 publications

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“…To eliminate the clock duty-cycle errors in memory interface channels, input clock buffers, and on-chip clock trees, typical high-speed DRAM and memory controllers utilize analog-type, digital-type or hybrid-type duty-cycle corrector (DCC) circuits [1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. The DCCs in DDR3, DDR4, LPDDR4, LPDDR5, and GDDR5 SDRAM applications performs duty-cycle error compensation of high-speed signal pins for a differential clock (CK/CKb), data signals (DQs), and a data strobe signal (DQS).…”

Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

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This Letter presents a 0.8-3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8-3.4 GHz. The duty-cycle correction range is ²15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm 2 .

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Section: Introductionmentioning

confidence: 99%

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Hwang

Kim

2019

IEICE Electron. Express

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“…However, researches on high-speed DCC circuits are still rare. For most conventional DCC circuits, the highest clock frequency is limited to about 5-8 GHz [11], [12]. IBM integrated a 14 GHz DCC in its 28 Gb/s SerDes transmitter [13].…”

Section: Introductionmentioning

confidence: 99%

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector

Guo

Liu

Wang

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are used to support the DCC to work at a high frequency up to 20 GHz with a wide correction range from 20% to 80%. On the feedback path, a second order duty cycle detector scheme is adopted including a low pass filter and an integrator to significantly reduce the jitter in the output clock and ensure high correction accuracy. Through simulation using 65 nm TSMC CMOS technology, the output duty cycle is corrected to 50±0.3% over the input duty-cycle range of 20-80% for 12.5-20 GHz. The DCC consumes 5.2 mW at 16 GHz using a 1.0 V supply voltage, and has a 572 fs peak-to-peak jitter and a 249 fs RMS jitter.

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