A wideband sigma-delta phase-locked-loop modulator for wireless applications

Fahim, Amr; Elmasry, M.I.

doi:10.1109/tcsii.2003.809709

Cited by 26 publications

(21 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As mentioned before, frequency synthesizers are used to produce a stable and precise local oscillator frequency for channel switching and are one of the most important blocks for wireless transceiver. In the wireless transceiver system, the frequency synthesizer lock time should be less than the required time for channel switching according to the wireless standards [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. For voice and data communication, there are many standards which define how devices communicate with each other.…”

Section: Lock Time For Ds-fn-pll Frequency Synthesizermentioning

confidence: 99%

“…In today's wireless systems, the frequency synthesizer should satisfy both conditions that are narrow channel spacing (high frequency resolution) for spectrum concerns and fast switching time between frequencies (low settling/lock time) for high speed requirements. By deploying a dual modulus FN Phase Locked Loop (PLL) as depicted in Figure 1, it is possible to solve and eliminate these two conflicting problems by providing increased reference frequency and Loop Filter (LF) bandwidth [1]- [2]. In FN-PLL synthesizer, the division ratio can be any number and is not restricted to be an integer as in the case of Integer-N PLL frequency synthesizer.…”

Section: Introductionmentioning

confidence: 99%

“…By randomizing the frequency division ratio in the loop to get rid of reference frequency spurs, the quantization noise of the fractional-divider can be pushed away to the higher frequencies by the aid of using DSMs [1]- [2]. This type of FN-PLL frequency synthesizer is called as a Delta-Sigma FN-PLL (DS-FN-PLL) frequency synthesizer and its general block diagram is given in Figure 2.…”

Section: Introductionmentioning

confidence: 99%

“…In DS-FN-PLL synthesizer applications, the input of the DSM (fractional part of the division ratio) is always constant, DC. A DSM is a nonlinear system and it is well known that it produces spurs for DC inputs [2] - [3]. By increasing the order of the MASH modulator, the in-band tones can be effectively suppressed.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

Telli

Kale

2009

2009 IEEE 10th Annual Wireless and Microwave Technology Conference

View full text Add to dashboard Cite

Section: Lock Time For Ds-fn-pll Frequency Synthesizermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

Telli

Kale

2009

2009 IEEE 10th Annual Wireless and Microwave Technology Conference

View full text Add to dashboard Cite

“…The utilization of digital ∆Σ is not limited to digital-to-analog conversion only. It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

View full text Add to dashboard Cite

Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

show abstract

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Mao

Yang

Wang

2006

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigmadelta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the inband phase noise reduction of the sigma-delta frequency synthesizer.

show abstract

A wideband sigma-delta phase-locked-loop modulator for wireless applications

Cited by 26 publications

References 10 publications

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

Complexity and Power Reduction in Digital Delta-Sigma Modulators

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Contact Info

Product

Resources

About