A Zero Phase-Lag Homodyne Demodulation Technique for Synchronous Measurement Applications and Its Fpga Implementation

Abstract

A simple homodyne direct digital demodulation technique that is insensitive to sensor induced phase-error and its innovative FPGA implementation are presented here. This novel demodulation scheme does not need a low pass filter; thereby the inherent filter time lag is eliminated. A direct digital read-out of the demodulated signal, i.e., the measurand value, is obtained through analog-to-digital conversion of the modulated signal at an instant that coincides with its peak. This peak sampling eliminates the processor time required in quadrature demodulators to obtain the measurand from the in-phase and quadrature components. For this purpose a quadrature square wave is first generated from the reference carrier. Digital measures of carrier time period and sensor induced time lag/lead are used to ensure that the rising edges of this quadrature square wave coincide with the peak instants of the modulated signal. The required sampling instants for digitization of the modulated signal are generated in synchronism with its rising edges. The digital read-out of the measurand is directly obtained without taking recourse to the standard sequence of multiplication, low-pass filtering and the subsequent processing common in existing synchronous phase-sensitive demodulators. With an a priori knowledge of the sensor-type used, this innovative FPGA-based implementation accommodates sensors introducing lagging or leading phase-shift in the modulated carrier.