Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies

Sketopoulos, Nikolaos; Sotiriou, Christos; Simoglou, Stavros

doi:10.23919/date.2018.8342243

Cited by 6 publications

(2 citation statements)

References 13 publications

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“…Therefore, most approaches are based on the Greedy BBFM (GBBFM) approach. An alternative 3D partition approach has been proposed in [3], [10]. A 3D Legalisation Algorithm (3DLG) is utilized, where the cutsize may or may not be constrained.…”

Section: A 3dic Tier Partitioningmentioning

confidence: 99%

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Sketopoulos

Sotiriou

Pavlidis

2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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In this work, we investigate the effect of metal stack and tier 3D IC partitioning methodologies on the Quality of Results (QoR) of monolithic 3D circuits compared to their 2D counterparts. Two interconnect options are considered. For the interconnect option, termed Single, a single metal stack is used where cell pins lie on two lower metal layers. A Face to Face (F2F) interconnect option is also considered where cell pins lie on symmetrical lower and upper metal layers in two different tiers. In addition, two 3D circuit partitioning methodologies are investigated including the Greedy Bin-Based Fidducia-Mattheyses (GBBFM) and a Displacement-based 3D Legaliser (3DLG). For both the 2D and 3D circuits, a multi-pass timing-driven In-Place Optimisation (IPO) is performed with an industrial P&R tool to extract the best QoR. For the 3D circuits, the IPO is applied after tier partitioning. The 45 nm nanoCAS library, a 3D library based on NANGATE 45 nm, is utilized and three typical benchmark circuits are analysed. The performance of 3D circuits is improved between 1% to 3%, total wirelength is significantly reduced, via usage is increased, yet the estimated power and cell area do not necessarily decrease. Single metal stack overall demonstrates better QoR than F2F integration.

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Section: A 3dic Tier Partitioningmentioning

confidence: 99%

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Sketopoulos

Sotiriou

Pavlidis

2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…In the literature [15], the authors tackle placement induced problems, such as pin shorts and pin access, by adopting a look-ahead legalization procedure that ensures the existence of sufficient white space among cells. Abax [16] is another legalizer contrived from Abacus. While it retains the main functionality of Abacus, Abax adds hard-macro/blockage handling capabilities and look-ahead legalization during the global placement step, tailored to suit the minimization of the mean displacement function.…”

Section: Related Workmentioning

confidence: 99%

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

et al. 2018

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In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

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Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL

Georgakidis

Sotiriou

2020

2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abax: 2D/3D legaliser supporting look-ahead legalisation and blockage strategies

Cited by 6 publications

References 13 publications

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Metal Stack and Partitioning Exploration for Monolithic 3D ICs

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL

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