About the functional test of the GPGPU scheduler

Du, Boyang; Condia, Josie E. Rodriguez; Reorda, M. Sonza; Sterpone, Luca

doi:10.1109/iolts.2018.8474174

Cited by 16 publications

(8 citation statements)

References 9 publications

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“…Moreover, this work introduced some mitigation strategies targeting permanent faults during the in-field execution of the GPGPU. In [38], some first techniques tested and detected permanent faults in the SC of the GPGPU and its internal memory. Finally, authors in [39] recently proposed some methods for periodic on-line testing of the execution units (or Scalar Processors (SPs)) in the SM by generating a divergence path and executing partial workloads of a test program.…”

Section: Related Work In the Areamentioning

confidence: 99%

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An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

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Section: Related Work In the Areamentioning

confidence: 99%

“…In the present work, we remove multiple limitations presented in some previous works [38], [40]. In [38], a set of proposed incremental functional test techniques targeted the detection of faults in single memory cells of the SC. The assembly language of the GPGPU described each proposed method during the implementation phase.…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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“…Furthermore, this is a critical unit during the GPGPU operation and a fault can generate misbehaviors generating hang or SDC effects. This module is selected by its criticality in thread execution and the sensitivity to permanent faults observed in other works [18]. For the purpose of this work, we target the warp pool memory in the scheduler injecting SEU faults in it and classifying its sensitivity to them.…”

Section: B Target Modulesmentioning

confidence: 99%

On the evaluation of SEU effects in GPGPUs

Condia

Reorda

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

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1-General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video processing thanks to their powerful parallel architecture. In the last years, GPGPUs have been considered also for safety-critical applications, such as autonomous and semi-autonomous car driving systems. New GPGPU devices include an increasing number of parallel cores in order to increase throughput and performance. This increment in the number of cores and the requirements in terms of power consumption force designers to use aggressive semiconductor technologies. Nevertheless, those new devices can be seriously affected by radiation effects, modeled as Single Event Upsets (SEUs). SEUs could generate unexpected operation effects in the applications which could be unacceptable for the safety-critical ones. This work analyzes the SEU effects resorting to an open-source model of a GPGPU based on the Nvidia's G80 architecture and aims at complementing previous analysis based on radiation experiments.

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“…Our work exploited an open-source VHDL GPGPU model (named FlexGrip) of the G80 architecture of NVIDIA [3]. In [4] we proposed some first works targeting the warp scheduler in a GPGPU. In [5], we presented an SBST approach to detect permanent faults in the pipeline registers (PRs) of a GPGPU and for the first time, we reported an experimental evaluation of its effectiveness, based on assessing the achieved FC.…”

Section: Introductionmentioning

confidence: 99%

Untestable faults identification in GPGPUs for safety-critical applications

Condia

Silva

Hamdioui

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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1-Nowadays, General Purpose Graphics Processing Units (GPGPUs) devices are considered as promising solutions for high-performance safety-critical applications, such as those in the automotive field. However, their adoption requires solutions to effectively detect faults arising in the device during the operative life. Hence, effective in-field test solutions are required to guarantee high-reliability levels. In this paper, we leverage the results of Software-Based Self-Test (SBST) based approaches for GPGPUs by deploying new techniques for automating the identification of untestable faults (UF). Our methodology has achieved fault coverage of 82.8% when applied to an open-source implementation of the NVIDIA G80 GPU architecture. The proposed approach combining SBSTs and UFs identification appears as an effective solution for the reliability analysis of GPGPUs.

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About the functional test of the GPGPU scheduler

Cited by 16 publications

References 9 publications

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

On the evaluation of SEU effects in GPGPUs

Untestable faults identification in GPGPUs for safety-critical applications

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