Ac-Dimm

Abstract

With technology scaling, on-chip power dissipation and offchip memory bandwidth have become significant performance bottlenecks in virtually all computer systems, from mobile devices to supercomputers. An effective way of improving performance in the face of bandwidth and power limitations is to rely on associative memory systems. Recent work on a PCM-based, associative TCAM accelerator shows that associative search capability can reduce both off-chip bandwidth demand and overall system energy. Unfortunately, previously proposed resistive TCAM accelerators have limited flexibility: only a restricted (albeit important) class of applications can benefit from a TCAM accelerator, and the implementation is confined to resistive memory technologies with a high dynamic range ( R High R Low ), such as PCM. This work proposes AC-DIMM, a flexible, high-performance associative compute engine built on a DDR3-compatible memory module. AC-DIMM addresses the limited flexibility of previous resistive TCAM accelerators by combining two powerful capabilities-associative search and processing in memory. Generality is improved by augmenting a TCAM system with a set of integrated, user programmable microcontrollers that operate directly on search results, and by architecting the system such that key-value pairs can be colocated in the same TCAM row. A new, bit-serial TCAM array is proposed, which enables the system to be implemented using STT-MRAM. AC-DIMM achieves a 4.2× speedup and a 6.5× energy reduction over a conventional RAM-based system on a set of 13 evaluated applications.

Compute in‐Memory with Non‐Volatile Elements for Neural Networks: A Review from a Co‐Design Perspective

“…[60,87,88] • Magnetic random access memory (MRAM), where the tunneling current between two ferromagnetic metals (separated by a dielectric) can be switched between two states by altering the direction of the magnetic domains in the metals. [89][90][91][92][93] • Ferroelectric memories, including two-terminal ferroelectric tunnel junctions (FTJs) and three-terminal ferroelectric transistors (FEFET), where device resistance is altered by electric-field-switchable polarization dipoles in a thin ferroelectric layer in the device stack. [94][95][96][97] For these memory candidates, we distinguish between three relevant CIM operation modes (note that the storage properties of the memory element should not be confused with the CIM modes.…”

DASH-CAM: Dynamic Approximate SearcH Content Addressable Memory for genome classification

“…Several CAM designs utilize emerging nonvolatile memories, such as STT-MRAM [17, 19], FeFET [58] and ReRAM [56, 57]. While such designs provide considerably higher density compared to SRAM, they suffer from high power consumption and limited endurance during write operations.…”

In-Memory Associative Processors: Tutorial, Potential, and Challenges

“…The interconnection matrix is a basic switching matrix that allows the AP rows to communicate in parallel either bitwise or wordwise. Recent works consider memristive crossbar arrays as switching matrix [19] instead of the conventional CMOS-based reduction tree, as in [6]- [8], which improve both 0.0014 @2nm 0.0014 @5nm 0.0014 @10nm 0.0032 @20nm 0.042 @5nm [24] Retention Time (Years) > 1, 000 > 1, 000 > 10 > 100 - † Transistor area is estimated to be 8 × 14λ 2 and λ = 2.5nm for 5nm technology node. The RD area is estimated to be 4 times the minimum dim.…”

“…APs have been developed and explored in the seventies and have not been recognized due to limitations in developing large memories [2]. During the last decade, APs have been revived due to two main reasons [6]- [8]: 1) the emerging device technologies that enable high density and fast access time, and 2) the recent data-extensive applications such machine learning, visual computing, and natural language processing.…”