AC_ICAP: A Flexible High Speed ICAP Controller

Cardona, Luis Andres; Ferrer, Carles

doi:10.1155/2015/314358

Cited by 18 publications

(23 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Figure 4 shows the floor plan for RP_0 and RP_1 in Xilinx PlanAhead. 3.05600 DRAM DPR Manager [22] 3.07432 SD Flash FlashCAP [23] 3.08000 BRAM Intelligent ICAP Controller [24] 3.19832 SRAM ICAP Controller [25] 3.19840 DDR SDRAM BRAM_HWICAP [26] 2.97120 BRAM AC_ICAP [27] 3…”

Section: Discussionmentioning

confidence: 99%

An FPGA-based network system with service-uninterrupted remote functional update

Tan

Ooi

Marsono

2021

IJECE

View full text Add to dashboard Cite

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.

show abstract

Section: Discussionmentioning

confidence: 99%

An FPGA-based network system with service-uninterrupted remote functional update

Tan

Ooi

Marsono

2021

IJECE

View full text Add to dashboard Cite

show abstract

“…Another important part of the voter design is the use of the internal configuration access port (ICAP) and its associated controller [22]; ICAP has direct access to the FPGA configuration memory. ICAP is a primitive used for DPR.…”

Section: Proposed Designmentioning

confidence: 99%

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

View full text Add to dashboard Cite

Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

show abstract

“…International Journal of Reconfigurable Computing processor. ere are several similar designs along these lines [8][9][10][11]. A variant of this approach is to provide integrated extensibility of a general-purpose processor via DPR such as in [12].…”

Section: Related Workmentioning

confidence: 99%

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Kirchhoff

Kerling

Streitferdt

et al. 2019

International Journal of Reconfigurable Computing

View full text Add to dashboard Cite

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

show abstract

AC_ICAP: A Flexible High Speed ICAP Controller

Cited by 18 publications

References 18 publications

An FPGA-based network system with service-uninterrupted remote functional update

An FPGA-based network system with service-uninterrupted remote functional update

FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Contact Info

Product

Resources

About