Accelerating Maximum Likelihood Based Phylogenetic Kernels Using Network-on-Chip

Majumder, Turbo; Pande, Partha Pratim; Kalyanaraman, Ananth

doi:10.1109/sbac-pad.2011.17

Cited by 5 publications

(2 citation statements)

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“…For instance, a typical genome assembly algorithm farms out billions of pairwise sequence alignment tasks, each of which aligns two strings of small lengths (e.g., 100-500 base pairs) and can use a small number of cores (e.g., 8-16) [112]. As another example, consider the problem of computing phylogenetic inference using maximum likelihood (ML) [113], where one typically needs to carry out billions of independent tree evaluations, each of which internally performs a small number of floating point calculations using a few cores. In such applications, enhancing overall throughput in computation translates to shorter time to solution.…”

Section: Application Use-case Modelmentioning

confidence: 99%

On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications

Majumder¹,

Pande²,

Kalyanaraman³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Large-scale integration of multiple cores on a single chip is the current answer to the challenge of attaining higher computation throughput while restricting power consumption within acceptable limits. Network-on-Chip (NoC) is an emerging paradigm that can efficiently support integration of a massive number of cores on a chip by decoupling the on-chip computation and communication infrastructure, thereby overcoming scalability issues faced by conventional buses.Many scientific computing disciplines, such as computational biology, have seen a significant increase in the availability of parallel algorithms and highperformance computing (HPC) tools owing to high runtime complexities and/or the data-intensive nature underlying the computation. Software-only solutions are likely to be inadequate, creating the need for hardware accelerators. This dissertation explores the design and development of highly optimized NoC-based hardware accelerators for a particular class of biocomputing applications, viz. phylogeny reconstruction, which is important for evolutionary inferences in computational biology. This dissertation focuses on two computationally distinct phylogeny reconstruction approaches to demonstrate that NoC-based many-core platforms can deliver orders of magnitude reduction in time-to-solution, compared to v existing approaches. The Maximum Parsimony (MP) phylogeny reconstruction problem can be reduced to one of solving numerous instances of the classical Traveling Salesman Problem (TSP). 99% of the total software runtime is spent in computing TSP instances, whose solution typically involves an application of branch-and-bound runtime heuristics. This dissertation presents the design of many-core systems with core-level pipelined micro-parallel architecture and different interconnection topologies to achieve significant speedup and energy efficiency. In Maximum Likelihood (ML) phylogeny reconstruction, the improved quality of result comes at a higher computational cost, as this approach involves optimization over multi-dimensional real continuous space. We present NoCbased hardware accelerators that target function kernels contributing to a bulk of the runtime. These platforms combine novel ideas and approaches, such as space-filling Hilbert curves, parallelized core allocation schemes, and 3-D integration. We also explore the use of long-range on-chip wireless links on existing regular topologies to reduce network diameter, thereby reducing the average communication latency between cores. These platforms have the potential to serve a broader class of throughput-oriented HPC applications. viTable of Contents

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Section: Application Use-case Modelmentioning

confidence: 99%

On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications

Majumder¹,

Pande²,

Kalyanaraman³

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

Self Cite

View full text Add to dashboard Cite

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“…Expectedly, numerous efforts have been made to accelerate the PLF, employing various technologies, from multi-core processors [20,21] and supercomputers [22,23], to FPGAs [24,25] and GPUs [19,26], to CGRA-based solutions [27,28] and dedicated NoCs [29,30]. These efforts, however, predominantly concentrated on accelerating computation, thus remaining bounded by the memory accesses since the PLF is a data-intensive, memory-bound operation.…”

Section: Introductionmentioning

confidence: 99%

Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing

Alachiotis

Skrimponis

Pissadakis

et al. 2021

ACM Trans. Reconfigurable Technol. Syst.

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Disaggregated computer architectures eliminate resource fragmentation in next-generation datacenters by enabling virtual machines to employ resources such as CPUs, memory, and accelerators that are physically located on different servers. While this paves the way for highly compute- and/or memory-intensive applications to potentially deploy all CPUs and/or memory resources in a datacenter, it poses a major challenge to the efficient deployment of hardware accelerators: input/output data can reside on different servers than the ones hosting accelerator resources, thereby requiring time- and energy-consuming remote data transfers that diminish the gains of hardware acceleration. Targeting a disaggregated datacenter architecture similar to the IBM dReDBox disaggregated datacenter prototype, the present work explores the potential of deploying custom acceleration units adjacently to the disaggregated-memory controller on memory bricks (in dReDBox terminology), which is implemented on FPGA technology, to reduce data movement and improve performance and energy efficiency when reconstructing large phylogenies (evolutionary relationships among organisms). A fundamental computational kernel is the Phylogenetic Likelihood Function (PLF), which dominates the total execution time (up to 95%) of widely used maximum-likelihood methods. Numerous efforts to boost PLF performance over the years focused on accelerating computation; since the PLF is a data-intensive, memory-bound operation, performance remains limited by data movement, and memory disaggregation only exacerbates the problem. We describe two near-memory processing models, one that addresses the problem of workload distribution to memory bricks, which is particularly tailored toward larger genomes (e.g., plants and mammals), and one that reduces overall memory requirements through memory-side data interpolation transparently to the application, thereby allowing the phylogeny size to scale to a larger number of organisms without requiring additional memory.

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