Accelerating Monte Carlo based SSTA using FPGA

Cong, Jason; Gururaj, Karthik; Liu, Bin; Minkovich, Kirill; Yuan, Bo; Zou, Yi

doi:10.1145/1723112.1723132

Cited by 12 publications

(10 citation statements)

References 5 publications

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“…The hardware area of the proposed architecture is determined only by the number of STA-PEs run in parallel. It is also noteworthy that the proposed architecture can be implemented on non-configurable platforms, such as on ASIC, since the proposed hardware engine is netlist independent, while the previous architectures [13], [14] require configurable platform due to their netlist-dependence.…”

Section: Comparison With Conventional Methodsmentioning

confidence: 99%

“…In the existing studies [13], [14], [17], it is assumed that the delay samples are represented by normal distributions. To compare the proposed scheme with these studies, we use normally distributed delay variations in applying MC-SSTA.…”

Section: Timing Analysis For Gate Delaymentioning

confidence: 99%

“…However, it requires long time to map the RTL description into a target FPGA device. Other FPGA-based acceleration methods [14] may also suffer from this problem. The amount of hardware resources also imposes a limitation on the applicability of MC-SSTA, since the required hardware resources is proportional to the size of the input netlist.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

Yuasa

Tsutsui

Ochi

et al. 2013

IEICE Trans. Electron.

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We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than ×10 is achieved compared to conventional methods including GPU implementation. key words: statistical static timing analysis, delay distribution, slew rate, field-programmable gate array, Mersenne Twister

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Section: Comparison With Conventional Methodsmentioning

confidence: 99%

Section: Timing Analysis For Gate Delaymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

Yuasa

Tsutsui

Ochi

et al. 2013

IEICE Trans. Electron.

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“…At the circuit level, statistical techniques have been developed, which analyze the impact of variations on the clock frequency [7] and power consumption [19] of system components. Recent efforts have also looked at utilizing HW accelerators, such as FPGAs [20] and GPUs [21] to help accelerate these statistical techniques. Our use of FPGA platforms is very different in that we do not use it as an HW accelerator for timing analysis but instead use it to emulate the SoC in a cycle accurate manner.…”

Section: Related Workmentioning

confidence: 99%

Emulation-Based Analysis of System-on-Chip Performance Under Variations

Kozhikkottu

Venkatesan

Raghunathan

et al. 2016

IEEE Trans. VLSI Syst.

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The scaling of integrated circuits into the nanometer regime has led to variations emerging as a primary design concern. Most efforts in the area of variation-tolerant design have focused on the physical, circuit, and logic levels of abstraction. However, inevitable increases in the magnitude of variations with scaling have elevated them to a design concern that must be addressed starting at the system level. We address the problem of analyzing the performance of system-onchip (SoC) architectures in the presence of variations. A modern SoC is a complex ensemble of components that are organized into multiple voltage and frequency domains or islands. The impact of variations on the clock frequencies of individual SoC components may be analyzed using existing tools, such as circuit-level statistical timing analysis. However, the key challenge that needs to be addressed is how to translate these component-level clock frequency distributions into a system-level performance distribution. This task is particularly complex and challenging due to the interdependences between components' execution, indirect effects of shared resources, and interactions between multiple system-level execution paths. We argue that an accurate variation-aware performance analysis requires Monte Carlo-based repeated system execution. We describe a framework variability emulation for SoC performance analysis (VESPA)-that leverages emulation to significantly speed up the performance analysis without sacrificing the generality and accuracy achieved by Monte Carlo-based simulation. We further improve the efficiency of VESPA by utilizing correlated sampling to reduce the number of samples needed for Monte Carlo simulations. We demonstrate the utility of VESPA by applying it to design variation-tolerant architectures for three example SoCs. Our experiments show the performance improvements of ∼180× compared with the state-of-the-art hardware-software cosimulation tools and also underscore the potential of VESPA to enable variation-aware design and exploration at the system level.

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“…The efficient approach which utilizes low discrepancy random numbers, Latin hypercube sampling are discussed [13], Non parametric max/min operations based on Mann-Whitney statistics is defined to propagate efficient timing vectors [12]. More distinguished approach is given in Monte Carlo based SSTA [14].…”

Section: Introductionmentioning

confidence: 99%

A Fully Pipelined Power-Optimization Implementation of Monte Carlo Based SSTA on FPGA

Rao¹

2013

IOSR-JVSP

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Accelerating Monte Carlo based SSTA using FPGA

Cited by 12 publications

References 5 publications

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element

Emulation-Based Analysis of System-on-Chip Performance Under Variations

A Fully Pipelined Power-Optimization Implementation of Monte Carlo Based SSTA on FPGA

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