Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform

Biswas, Prasenjit; Udupa, Pramod; Mondal, Rajdeep; Varadarajan, Keshavan; Alle, Mythri; Nandy, S. K.; Narayan, Ranjani

doi:10.1109/isvlsi.2010.65

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Cited by 5 publications

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“…REDEFINE is an architecture framework from which domain specific accelerators can be derived. The performance advantage of REDEFINE over FPGAs and General Purpose Processors can be found in [2], [4].…”

Section: Introductionmentioning

confidence: 99%

Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture

Prashank

Prasadarao

Dutta

et al. 2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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3GPP LongTerm Evolution (LTE) is targeted towards variable transmission bandwidths to improve universal mobile telecommunications. This requires support for variable point FFT/IFFT (128 through 4096). ASIC solutions, one for a particular FFT is not cost-effective, while DSP solutions are not performance-effective. We hence provide a solution on REDE-FINE, a dynamically reconfigurable platform, by appropriately characterizing the compute elements. We make use of the idle resources of REDEFINE to improve throughput by supporting multiple channels of FFT/IFFT.

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Section: Introductionmentioning

confidence: 99%